sky130_fd_sc_hd__clkdlybuf4s25¶
Clock Delay Buffer 4-stage 0.25um length inner stage gates
This is a stub of cell description file
Cell name: sky130_fd_sc_hd__clkdlybuf4s25
Type: cell
Verilog name: sky130_fd_sc_hd__clkdlybuf4s25
Library: sky130_fd_sc_hd
Inputs: 1 (A)
Outputs: 1 (X)