sky130_fd_sc_hd__and4bb

4-input AND, first two inputs inverted

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hd__and4bb

  • Type: cell

  • Verilog name: sky130_fd_sc_hd__and4bb

  • Library: sky130_fd_sc_hd

  • Inputs: 4 (A_N, B_N, C, D)

  • Outputs: 1 (X)

sky130_fd_sc_hd__and4bb symbols

../../../../../_images/sky130_fd_sc_hd__and4bb.symbol.svg
../../../../../_images/sky130_fd_sc_hd__and4bb.pp.symbol.svg

sky130_fd_sc_hd__and4bb schematic

../../../../../_images/sky130_fd_sc_hd__and4bb.schematic.svg

sky130_fd_sc_hd__and4bb GDSII layouts

../../../../../_images/sky130_fd_sc_hd__and4bb_1.svg

sky130_fd_sc_hd__and4bb_1

../../../../../_images/sky130_fd_sc_hd__and4bb_2.svg

sky130_fd_sc_hd__and4bb_2

../../../../../_images/sky130_fd_sc_hd__and4bb_4.svg

sky130_fd_sc_hd__and4bb_4