sky130_fd_sc_hd__a2bb2o

2-input AND, both inputs inverted, into first input, and 2-input AND into 2nd input of 2-input OR

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hd__a2bb2o

  • Type: cell

  • Verilog name: sky130_fd_sc_hd__a2bb2o

  • Library: sky130_fd_sc_hd

  • Inputs: 4 (A1_N, A2_N, B1, B2)

  • Outputs: 1 (X)

sky130_fd_sc_hd__a2bb2o symbols

../../../../../_images/sky130_fd_sc_hd__a2bb2o.symbol.svg
../../../../../_images/sky130_fd_sc_hd__a2bb2o.pp.symbol.svg

sky130_fd_sc_hd__a2bb2o schematic

../../../../../_images/sky130_fd_sc_hd__a2bb2o.schematic.svg

sky130_fd_sc_hd__a2bb2o GDSII layouts

../../../../../_images/sky130_fd_sc_hd__a2bb2o_1.svg

sky130_fd_sc_hd__a2bb2o_1

../../../../../_images/sky130_fd_sc_hd__a2bb2o_2.svg

sky130_fd_sc_hd__a2bb2o_2

../../../../../_images/sky130_fd_sc_hd__a2bb2o_4.svg

sky130_fd_sc_hd__a2bb2o_4