sky130_fd_sc_hd__a21bo

2-input AND into first input of 2-input OR, 2nd input inverted

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hd__a21bo

  • Type: cell

  • Verilog name: sky130_fd_sc_hd__a21bo

  • Library: sky130_fd_sc_hd

  • Inputs: 3 (A1, A2, B1_N)

  • Outputs: 1 (X)

sky130_fd_sc_hd__a21bo symbols

../../../../../_images/sky130_fd_sc_hd__a21bo.symbol.svg
../../../../../_images/sky130_fd_sc_hd__a21bo.pp.symbol.svg

sky130_fd_sc_hd__a21bo schematic

../../../../../_images/sky130_fd_sc_hd__a21bo.schematic.svg

sky130_fd_sc_hd__a21bo GDSII layouts

../../../../../_images/sky130_fd_sc_hd__a21bo_1.svg

sky130_fd_sc_hd__a21bo_1

../../../../../_images/sky130_fd_sc_hd__a21bo_2.svg

sky130_fd_sc_hd__a21bo_2

../../../../../_images/sky130_fd_sc_hd__a21bo_4.svg

sky130_fd_sc_hd__a21bo_4