:cell:`sky130_fd_sc_ms__sdlclkp` ================================ **Scan gated clock** *This is a stub of cell description file* - **Cell name**: :cell:`sky130_fd_sc_ms__sdlclkp` - **Type**: cell - **Verilog name**: sky130_fd_sc_ms__sdlclkp - **Library**: sky130_fd_sc_ms - **Inputs**: 3 (SCE, GATE, CLK) - **Outputs**: 1 (GCLK) :cell:`sky130_fd_sc_ms__sdlclkp` symbols ---------------------------------------- .. list-table:: * - .. figure:: sky130_fd_sc_ms__sdlclkp.symbol.svg - - .. figure:: sky130_fd_sc_ms__sdlclkp.pp.symbol.svg :cell:`sky130_fd_sc_ms__sdlclkp` schematic ------------------------------------------ .. figure:: sky130_fd_sc_ms__sdlclkp.schematic.svg :align: center :cell:`sky130_fd_sc_ms__sdlclkp` GDSII layouts ---------------------------------------------- .. figure:: sky130_fd_sc_ms__sdlclkp_1.svg :align: center :width: 50% sky130_fd_sc_ms__sdlclkp_1 .. figure:: sky130_fd_sc_ms__sdlclkp_2.svg :align: center :width: 50% sky130_fd_sc_ms__sdlclkp_2 .. figure:: sky130_fd_sc_ms__sdlclkp_4.svg :align: center :width: 50% sky130_fd_sc_ms__sdlclkp_4