:cell:`sky130_fd_sc_ms__o41ai`
==============================

**4-input OR into 2-input NAND**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ms__o41ai`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ms__o41ai
-  **Library**: sky130_fd_sc_ms
-  **Inputs**:  5 (A1, A2, A3, A4, B1)
-  **Outputs**: 1 (Y)

:cell:`sky130_fd_sc_ms__o41ai` symbols
--------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_ms__o41ai.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ms__o41ai.pp.symbol.svg

:cell:`sky130_fd_sc_ms__o41ai` schematic
----------------------------------------

.. figure:: sky130_fd_sc_ms__o41ai.schematic.svg
    :align: center

:cell:`sky130_fd_sc_ms__o41ai` GDSII layouts
--------------------------------------------



.. figure:: sky130_fd_sc_ms__o41ai_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__o41ai_1


.. figure:: sky130_fd_sc_ms__o41ai_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__o41ai_2


.. figure:: sky130_fd_sc_ms__o41ai_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__o41ai_4