:cell:`sky130_fd_sc_ms__o2bb2ai`
================================

**2-input NAND and 2-input OR into 2-input NAND**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ms__o2bb2ai`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ms__o2bb2ai
-  **Library**: sky130_fd_sc_ms
-  **Inputs**:  4 (A1_N, A2_N, B1, B2)
-  **Outputs**: 1 (Y)

:cell:`sky130_fd_sc_ms__o2bb2ai` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_ms__o2bb2ai.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ms__o2bb2ai.pp.symbol.svg

:cell:`sky130_fd_sc_ms__o2bb2ai` schematic
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.. figure:: sky130_fd_sc_ms__o2bb2ai.schematic.svg
    :align: center

:cell:`sky130_fd_sc_ms__o2bb2ai` GDSII layouts
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.. figure:: sky130_fd_sc_ms__o2bb2ai_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__o2bb2ai_1


.. figure:: sky130_fd_sc_ms__o2bb2ai_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__o2bb2ai_2


.. figure:: sky130_fd_sc_ms__o2bb2ai_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__o2bb2ai_4