:cell:`sky130_fd_sc_ms__dlymetal6s2s`
=====================================

**6-inverter delay with output from 2nd stage on horizontal route**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ms__dlymetal6s2s`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ms__dlymetal6s2s
-  **Library**: sky130_fd_sc_ms
-  **Inputs**:  1 (A)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_ms__dlymetal6s2s` symbols
---------------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_ms__dlymetal6s2s.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ms__dlymetal6s2s.pp.symbol.svg

:cell:`sky130_fd_sc_ms__dlymetal6s2s` schematic
-----------------------------------------------

.. figure:: sky130_fd_sc_ms__dlymetal6s2s.schematic.svg
    :align: center

:cell:`sky130_fd_sc_ms__dlymetal6s2s` GDSII layouts
---------------------------------------------------



.. figure:: sky130_fd_sc_ms__dlymetal6s2s_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__dlymetal6s2s_1