:cell:`sky130_fd_sc_ms__clkdlyinv3sd3`
======================================

**Clock Delay Inverter 3-stage 0.50um length inner stage gate**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ms__clkdlyinv3sd3`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ms__clkdlyinv3sd3
-  **Library**: sky130_fd_sc_ms
-  **Inputs**:  1 (A)
-  **Outputs**: 1 (Y)

:cell:`sky130_fd_sc_ms__clkdlyinv3sd3` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_ms__clkdlyinv3sd3.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ms__clkdlyinv3sd3.pp.symbol.svg

:cell:`sky130_fd_sc_ms__clkdlyinv3sd3` schematic
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.. figure:: sky130_fd_sc_ms__clkdlyinv3sd3.schematic.svg
    :align: center

:cell:`sky130_fd_sc_ms__clkdlyinv3sd3` GDSII layouts
----------------------------------------------------



.. figure:: sky130_fd_sc_ms__clkdlyinv3sd3_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__clkdlyinv3sd3_1