:cell:`sky130_fd_sc_ms__a2111oi`
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**2-input AND into first input of 4-input NOR**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ms__a2111oi`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ms__a2111oi
-  **Library**: sky130_fd_sc_ms
-  **Inputs**:  5 (A1, A2, B1, C1, D1)
-  **Outputs**: 1 (Y)

:cell:`sky130_fd_sc_ms__a2111oi` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_ms__a2111oi.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ms__a2111oi.pp.symbol.svg

:cell:`sky130_fd_sc_ms__a2111oi` schematic
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.. figure:: sky130_fd_sc_ms__a2111oi.schematic.svg
    :align: center

:cell:`sky130_fd_sc_ms__a2111oi` GDSII layouts
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.. figure:: sky130_fd_sc_ms__a2111oi_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__a2111oi_1


.. figure:: sky130_fd_sc_ms__a2111oi_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__a2111oi_2


.. figure:: sky130_fd_sc_ms__a2111oi_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__a2111oi_4