:cell:`sky130_fd_sc_ls__sedfxtp`
================================

**Scan delay flop, data enable, non-inverted clock, single output**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ls__sedfxtp`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ls__sedfxtp
-  **Library**: sky130_fd_sc_ls
-  **Inputs**:  5 (CLK, D, DE, SCD, SCE)
-  **Outputs**: 1 (Q)

:cell:`sky130_fd_sc_ls__sedfxtp` symbols
----------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_ls__sedfxtp.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ls__sedfxtp.pp.symbol.svg

:cell:`sky130_fd_sc_ls__sedfxtp` schematic
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.. figure:: sky130_fd_sc_ls__sedfxtp.schematic.svg
    :align: center

:cell:`sky130_fd_sc_ls__sedfxtp` GDSII layouts
----------------------------------------------



.. figure:: sky130_fd_sc_ls__sedfxtp_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__sedfxtp_1


.. figure:: sky130_fd_sc_ls__sedfxtp_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__sedfxtp_2


.. figure:: sky130_fd_sc_ls__sedfxtp_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__sedfxtp_4