:cell:`sky130_fd_sc_ls__o211ai`
===============================

**2-input OR into first input of 3-input NAND**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ls__o211ai`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ls__o211ai
-  **Library**: sky130_fd_sc_ls
-  **Inputs**:  4 (A1, A2, B1, C1)
-  **Outputs**: 1 (Y)

:cell:`sky130_fd_sc_ls__o211ai` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_ls__o211ai.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ls__o211ai.pp.symbol.svg

:cell:`sky130_fd_sc_ls__o211ai` schematic
-----------------------------------------

.. figure:: sky130_fd_sc_ls__o211ai.schematic.svg
    :align: center

:cell:`sky130_fd_sc_ls__o211ai` GDSII layouts
---------------------------------------------



.. figure:: sky130_fd_sc_ls__o211ai_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__o211ai_1


.. figure:: sky130_fd_sc_ls__o211ai_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__o211ai_2


.. figure:: sky130_fd_sc_ls__o211ai_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__o211ai_4