:cell:`sky130_fd_sc_ls__ha`
===========================

**Half adder**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ls__ha`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ls__ha
-  **Library**: sky130_fd_sc_ls
-  **Inputs**:  2 (A, B)
-  **Outputs**: 2 (COUT, SUM)

:cell:`sky130_fd_sc_ls__ha` symbols
-----------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_ls__ha.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ls__ha.pp.symbol.svg

:cell:`sky130_fd_sc_ls__ha` schematic
-------------------------------------

.. figure:: sky130_fd_sc_ls__ha.schematic.svg
    :align: center

:cell:`sky130_fd_sc_ls__ha` GDSII layouts
-----------------------------------------



.. figure:: sky130_fd_sc_ls__ha_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__ha_1


.. figure:: sky130_fd_sc_ls__ha_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__ha_2


.. figure:: sky130_fd_sc_ls__ha_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__ha_4