:cell:`sky130_fd_sc_ls__fahcin`
===============================

**Full adder, inverted carry in**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ls__fahcin`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ls__fahcin
-  **Library**: sky130_fd_sc_ls
-  **Inputs**:  3 (A, B, CIN)
-  **Outputs**: 2 (COUT, SUM)

:cell:`sky130_fd_sc_ls__fahcin` symbols
---------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_ls__fahcin.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ls__fahcin.pp.symbol.svg

:cell:`sky130_fd_sc_ls__fahcin` schematic
-----------------------------------------

.. figure:: sky130_fd_sc_ls__fahcin.schematic.svg
    :align: center

:cell:`sky130_fd_sc_ls__fahcin` GDSII layouts
---------------------------------------------



.. figure:: sky130_fd_sc_ls__fahcin_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__fahcin_1