:cell:`sky130_fd_sc_ls__clkbuf`
===============================

**Clock tree buffer**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ls__clkbuf`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ls__clkbuf
-  **Library**: sky130_fd_sc_ls
-  **Inputs**:  1 (A)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_ls__clkbuf` symbols
---------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_ls__clkbuf.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ls__clkbuf.pp.symbol.svg

:cell:`sky130_fd_sc_ls__clkbuf` schematic
-----------------------------------------

.. figure:: sky130_fd_sc_ls__clkbuf.schematic.svg
    :align: center

:cell:`sky130_fd_sc_ls__clkbuf` GDSII layouts
---------------------------------------------



.. figure:: sky130_fd_sc_ls__clkbuf_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__clkbuf_1


.. figure:: sky130_fd_sc_ls__clkbuf_16.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__clkbuf_16


.. figure:: sky130_fd_sc_ls__clkbuf_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__clkbuf_2


.. figure:: sky130_fd_sc_ls__clkbuf_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__clkbuf_4


.. figure:: sky130_fd_sc_ls__clkbuf_8.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__clkbuf_8