:cell:`sky130_fd_sc_hs__tapvpwrvgnd`
====================================

**Substrate and well tap cell**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hs__tapvpwrvgnd`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hs__tapvpwrvgnd
-  **Library**: sky130_fd_sc_hs
-  **Inputs**:  0 ()
-  **Outputs**: 0 ()

:cell:`sky130_fd_sc_hs__tapvpwrvgnd` symbols
--------------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hs__tapvpwrvgnd.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hs__tapvpwrvgnd.pp.symbol.svg

:cell:`sky130_fd_sc_hs__tapvpwrvgnd` schematic
----------------------------------------------

.. figure:: sky130_fd_sc_hs__tapvpwrvgnd.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hs__tapvpwrvgnd` GDSII layouts
--------------------------------------------------



.. figure:: sky130_fd_sc_hs__tapvpwrvgnd_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hs__tapvpwrvgnd_1