:cell:`sky130_fd_sc_hs__o32a`
=============================

**3-input OR and 2-input OR into 2-input AND**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hs__o32a`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hs__o32a
-  **Library**: sky130_fd_sc_hs
-  **Inputs**:  5 (A1, A2, A3, B1, B2)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_hs__o32a` symbols
-------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hs__o32a.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hs__o32a.pp.symbol.svg

:cell:`sky130_fd_sc_hs__o32a` schematic
---------------------------------------

.. figure:: sky130_fd_sc_hs__o32a.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hs__o32a` GDSII layouts
-------------------------------------------



.. figure:: sky130_fd_sc_hs__o32a_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hs__o32a_1


.. figure:: sky130_fd_sc_hs__o32a_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hs__o32a_2


.. figure:: sky130_fd_sc_hs__o32a_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hs__o32a_4