:cell:`sky130_fd_sc_hs__o2111ai`
================================

**2-input OR into first input of 4-input NAND**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hs__o2111ai`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hs__o2111ai
-  **Library**: sky130_fd_sc_hs
-  **Inputs**:  5 (A1, A2, B1, C1, D1)
-  **Outputs**: 1 (Y)

:cell:`sky130_fd_sc_hs__o2111ai` symbols
----------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hs__o2111ai.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hs__o2111ai.pp.symbol.svg

:cell:`sky130_fd_sc_hs__o2111ai` schematic
------------------------------------------

.. figure:: sky130_fd_sc_hs__o2111ai.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hs__o2111ai` GDSII layouts
----------------------------------------------



.. figure:: sky130_fd_sc_hs__o2111ai_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hs__o2111ai_1


.. figure:: sky130_fd_sc_hs__o2111ai_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hs__o2111ai_2


.. figure:: sky130_fd_sc_hs__o2111ai_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hs__o2111ai_4