:cell:`sky130_fd_sc_hs__dlrtn`
==============================

**Delay latch, inverted reset, inverted enable, single output**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hs__dlrtn`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hs__dlrtn
-  **Library**: sky130_fd_sc_hs
-  **Inputs**:  3 (RESET_B, D, GATE_N)
-  **Outputs**: 1 (Q)

:cell:`sky130_fd_sc_hs__dlrtn` symbols
--------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hs__dlrtn.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hs__dlrtn.pp.symbol.svg

:cell:`sky130_fd_sc_hs__dlrtn` schematic
----------------------------------------

.. figure:: sky130_fd_sc_hs__dlrtn.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hs__dlrtn` GDSII layouts
--------------------------------------------



.. figure:: sky130_fd_sc_hs__dlrtn_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hs__dlrtn_1


.. figure:: sky130_fd_sc_hs__dlrtn_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hs__dlrtn_2


.. figure:: sky130_fd_sc_hs__dlrtn_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hs__dlrtn_4