:cell:`sky130_fd_sc_hdll__tapvpwrvgnd`
======================================

**Substrate and well tap cell**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__tapvpwrvgnd`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__tapvpwrvgnd
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  0 ()
-  **Outputs**: 0 ()

:cell:`sky130_fd_sc_hdll__tapvpwrvgnd` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__tapvpwrvgnd.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__tapvpwrvgnd.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__tapvpwrvgnd` schematic
------------------------------------------------

.. figure:: sky130_fd_sc_hdll__tapvpwrvgnd.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__tapvpwrvgnd` GDSII layouts
----------------------------------------------------



.. figure:: sky130_fd_sc_hdll__tapvpwrvgnd_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__tapvpwrvgnd_1