:cell:`sky130_fd_sc_hdll__sdfbbp`
=================================

**Scan delay flop, inverted set, inverted reset, non-inverted clock, complementary outputs**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__sdfbbp`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__sdfbbp
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  6 (D, SCD, SCE, CLK, SET_B, RESET_B)
-  **Outputs**: 2 (Q, Q_N)

:cell:`sky130_fd_sc_hdll__sdfbbp` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__sdfbbp.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__sdfbbp.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__sdfbbp` schematic
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.. figure:: sky130_fd_sc_hdll__sdfbbp.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__sdfbbp` GDSII layouts
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.. figure:: sky130_fd_sc_hdll__sdfbbp_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__sdfbbp_1