:cell:`sky130_fd_sc_hdll__or4`
==============================

**4-input OR**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__or4`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__or4
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  4 (A, B, C, D)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_hdll__or4` symbols
--------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__or4.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__or4.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__or4` schematic
----------------------------------------

.. figure:: sky130_fd_sc_hdll__or4.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__or4` GDSII layouts
--------------------------------------------



.. figure:: sky130_fd_sc_hdll__or4_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__or4_1


.. figure:: sky130_fd_sc_hdll__or4_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__or4_2


.. figure:: sky130_fd_sc_hdll__or4_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__or4_4