:cell:`sky130_fd_sc_hdll__nand2`
================================

**2-input NAND**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__nand2`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__nand2
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  2 (A, B)
-  **Outputs**: 1 (Y)

:cell:`sky130_fd_sc_hdll__nand2` symbols
----------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__nand2.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__nand2.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__nand2` schematic
------------------------------------------

.. figure:: sky130_fd_sc_hdll__nand2.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__nand2` GDSII layouts
----------------------------------------------



.. figure:: sky130_fd_sc_hdll__nand2_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__nand2_1


.. figure:: sky130_fd_sc_hdll__nand2_12.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__nand2_12


.. figure:: sky130_fd_sc_hdll__nand2_16.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__nand2_16


.. figure:: sky130_fd_sc_hdll__nand2_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__nand2_2


.. figure:: sky130_fd_sc_hdll__nand2_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__nand2_4


.. figure:: sky130_fd_sc_hdll__nand2_6.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__nand2_6


.. figure:: sky130_fd_sc_hdll__nand2_8.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__nand2_8