:cell:`sky130_fd_sc_hdll__inv`
==============================

**Inverter**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__inv`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__inv
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  1 (A)
-  **Outputs**: 1 (Y)

:cell:`sky130_fd_sc_hdll__inv` symbols
--------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__inv.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__inv.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__inv` schematic
----------------------------------------

.. figure:: sky130_fd_sc_hdll__inv.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__inv` GDSII layouts
--------------------------------------------



.. figure:: sky130_fd_sc_hdll__inv_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__inv_1


.. figure:: sky130_fd_sc_hdll__inv_12.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__inv_12


.. figure:: sky130_fd_sc_hdll__inv_16.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__inv_16


.. figure:: sky130_fd_sc_hdll__inv_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__inv_2


.. figure:: sky130_fd_sc_hdll__inv_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__inv_4


.. figure:: sky130_fd_sc_hdll__inv_6.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__inv_6


.. figure:: sky130_fd_sc_hdll__inv_8.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__inv_8