:cell:`sky130_fd_sc_hdll__diode`
================================

**Antenna tie-down diode**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__diode`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__diode
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  1 (DIODE)
-  **Outputs**: 0 ()

:cell:`sky130_fd_sc_hdll__diode` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__diode.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__diode.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__diode` schematic
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.. figure:: sky130_fd_sc_hdll__diode.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__diode` GDSII layouts
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.. figure:: sky130_fd_sc_hdll__diode_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__diode_2


.. figure:: sky130_fd_sc_hdll__diode_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__diode_4


.. figure:: sky130_fd_sc_hdll__diode_6.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__diode_6


.. figure:: sky130_fd_sc_hdll__diode_8.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__diode_8