:cell:`sky130_fd_sc_hdll__dfrtp`
================================

**Delay flop, inverted reset, single output**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__dfrtp`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__dfrtp
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  3 (CLK, D, RESET_B)
-  **Outputs**: 1 (Q)

:cell:`sky130_fd_sc_hdll__dfrtp` symbols
----------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__dfrtp.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__dfrtp.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__dfrtp` schematic
------------------------------------------

.. figure:: sky130_fd_sc_hdll__dfrtp.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__dfrtp` GDSII layouts
----------------------------------------------



.. figure:: sky130_fd_sc_hdll__dfrtp_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__dfrtp_1


.. figure:: sky130_fd_sc_hdll__dfrtp_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__dfrtp_2


.. figure:: sky130_fd_sc_hdll__dfrtp_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__dfrtp_4