:cell:`sky130_fd_sc_hdll__conb`
===============================

**Constant value, low, high outputs**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__conb`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__conb
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  0 ()
-  **Outputs**: 2 (HI, LO)

:cell:`sky130_fd_sc_hdll__conb` symbols
---------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__conb.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__conb.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__conb` schematic
-----------------------------------------

.. figure:: sky130_fd_sc_hdll__conb.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__conb` GDSII layouts
---------------------------------------------



.. figure:: sky130_fd_sc_hdll__conb_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__conb_1