:cell:`sky130_fd_sc_hdll__buf`
==============================

**Buffer**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__buf`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__buf
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  1 (A)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_hdll__buf` symbols
--------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__buf.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__buf.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__buf` schematic
----------------------------------------

.. figure:: sky130_fd_sc_hdll__buf.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__buf` GDSII layouts
--------------------------------------------



.. figure:: sky130_fd_sc_hdll__buf_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__buf_1


.. figure:: sky130_fd_sc_hdll__buf_12.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__buf_12


.. figure:: sky130_fd_sc_hdll__buf_16.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__buf_16


.. figure:: sky130_fd_sc_hdll__buf_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__buf_2


.. figure:: sky130_fd_sc_hdll__buf_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__buf_4


.. figure:: sky130_fd_sc_hdll__buf_6.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__buf_6


.. figure:: sky130_fd_sc_hdll__buf_8.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__buf_8