:cell:`sky130_fd_sc_hdll__and2`
===============================

**2-input AND**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__and2`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__and2
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  2 (A, B)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_hdll__and2` symbols
---------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__and2.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__and2.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__and2` schematic
-----------------------------------------

.. figure:: sky130_fd_sc_hdll__and2.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__and2` GDSII layouts
---------------------------------------------



.. figure:: sky130_fd_sc_hdll__and2_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__and2_1


.. figure:: sky130_fd_sc_hdll__and2_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__and2_2


.. figure:: sky130_fd_sc_hdll__and2_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__and2_4


.. figure:: sky130_fd_sc_hdll__and2_6.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__and2_6


.. figure:: sky130_fd_sc_hdll__and2_8.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__and2_8