:cell:`sky130_fd_sc_hdll__a221oi`
=================================

**2-input AND into first two inputs of 3-input NOR**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__a221oi`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__a221oi
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  5 (A1, A2, B1, B2, C1)
-  **Outputs**: 1 (Y)

:cell:`sky130_fd_sc_hdll__a221oi` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__a221oi.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__a221oi.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__a221oi` schematic
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.. figure:: sky130_fd_sc_hdll__a221oi.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__a221oi` GDSII layouts
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.. figure:: sky130_fd_sc_hdll__a221oi_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__a221oi_1


.. figure:: sky130_fd_sc_hdll__a221oi_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__a221oi_2


.. figure:: sky130_fd_sc_hdll__a221oi_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__a221oi_4