:cell:`sky130_fd_sc_hdll__a21bo`
================================

**2-input AND into first input of 2-input OR, 2nd input inverted**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__a21bo`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__a21bo
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  3 (A1, A2, B1_N)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_hdll__a21bo` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__a21bo.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__a21bo.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__a21bo` schematic
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.. figure:: sky130_fd_sc_hdll__a21bo.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__a21bo` GDSII layouts
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.. figure:: sky130_fd_sc_hdll__a21bo_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__a21bo_1


.. figure:: sky130_fd_sc_hdll__a21bo_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__a21bo_2


.. figure:: sky130_fd_sc_hdll__a21bo_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__a21bo_4