:cell:`sky130_fd_sc_hdll__a211o`
================================

**2-input AND into first input of 3-input OR**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__a211o`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__a211o
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  4 (A1, A2, B1, C1)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_hdll__a211o` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__a211o.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__a211o.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__a211o` schematic
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.. figure:: sky130_fd_sc_hdll__a211o.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__a211o` GDSII layouts
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.. figure:: sky130_fd_sc_hdll__a211o_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__a211o_1


.. figure:: sky130_fd_sc_hdll__a211o_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__a211o_2


.. figure:: sky130_fd_sc_hdll__a211o_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__a211o_4