:cell:`sky130_fd_sc_hd__sdfbbn`
===============================

**Scan delay flop, inverted set, inverted reset, inverted clock, complementary outputs**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hd__sdfbbn`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hd__sdfbbn
-  **Library**: sky130_fd_sc_hd
-  **Inputs**:  6 (D, SCD, SCE, CLK_N, SET_B, RESET_B)
-  **Outputs**: 2 (Q, Q_N)

:cell:`sky130_fd_sc_hd__sdfbbn` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_hd__sdfbbn.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hd__sdfbbn.pp.symbol.svg

:cell:`sky130_fd_sc_hd__sdfbbn` schematic
-----------------------------------------

.. figure:: sky130_fd_sc_hd__sdfbbn.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hd__sdfbbn` GDSII layouts
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.. figure:: sky130_fd_sc_hd__sdfbbn_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__sdfbbn_1


.. figure:: sky130_fd_sc_hd__sdfbbn_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__sdfbbn_2