:cell:`sky130_fd_sc_hd__or2`
============================

**2-input OR**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hd__or2`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hd__or2
-  **Library**: sky130_fd_sc_hd
-  **Inputs**:  2 (A, B)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_hd__or2` symbols
------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hd__or2.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hd__or2.pp.symbol.svg

:cell:`sky130_fd_sc_hd__or2` schematic
--------------------------------------

.. figure:: sky130_fd_sc_hd__or2.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hd__or2` GDSII layouts
------------------------------------------



.. figure:: sky130_fd_sc_hd__or2_0.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__or2_0


.. figure:: sky130_fd_sc_hd__or2_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__or2_1


.. figure:: sky130_fd_sc_hd__or2_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__or2_2


.. figure:: sky130_fd_sc_hd__or2_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__or2_4