:cell:`sky130_fd_sc_hd__o311a`
==============================

**3-input OR into 3-input AND**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hd__o311a`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hd__o311a
-  **Library**: sky130_fd_sc_hd
-  **Inputs**:  5 (A1, A2, A3, B1, C1)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_hd__o311a` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_hd__o311a.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hd__o311a.pp.symbol.svg

:cell:`sky130_fd_sc_hd__o311a` schematic
----------------------------------------

.. figure:: sky130_fd_sc_hd__o311a.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hd__o311a` GDSII layouts
--------------------------------------------



.. figure:: sky130_fd_sc_hd__o311a_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__o311a_1


.. figure:: sky130_fd_sc_hd__o311a_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__o311a_2


.. figure:: sky130_fd_sc_hd__o311a_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__o311a_4