:cell:`sky130_fd_sc_hd__o21bai`
===============================

**2-input OR into first input of 2-input NAND, 2nd iput inverted**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hd__o21bai`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hd__o21bai
-  **Library**: sky130_fd_sc_hd
-  **Inputs**:  3 (A1, A2, B1_N)
-  **Outputs**: 1 (Y)

:cell:`sky130_fd_sc_hd__o21bai` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_hd__o21bai.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hd__o21bai.pp.symbol.svg

:cell:`sky130_fd_sc_hd__o21bai` schematic
-----------------------------------------

.. figure:: sky130_fd_sc_hd__o21bai.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hd__o21bai` GDSII layouts
---------------------------------------------



.. figure:: sky130_fd_sc_hd__o21bai_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__o21bai_1


.. figure:: sky130_fd_sc_hd__o21bai_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__o21bai_2


.. figure:: sky130_fd_sc_hd__o21bai_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__o21bai_4