:cell:`sky130_fd_sc_hd__a41o`
=============================

**4-input AND into first input of 2-input OR**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hd__a41o`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hd__a41o
-  **Library**: sky130_fd_sc_hd
-  **Inputs**:  5 (A1, A2, A3, A4, B1)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_hd__a41o` symbols
-------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hd__a41o.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hd__a41o.pp.symbol.svg

:cell:`sky130_fd_sc_hd__a41o` schematic
---------------------------------------

.. figure:: sky130_fd_sc_hd__a41o.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hd__a41o` GDSII layouts
-------------------------------------------



.. figure:: sky130_fd_sc_hd__a41o_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__a41o_1


.. figure:: sky130_fd_sc_hd__a41o_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__a41o_2


.. figure:: sky130_fd_sc_hd__a41o_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__a41o_4