:cell:`sky130_fd_sc_hd__a2bb2oi`
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**2-input AND, both inputs inverted, into first input, and 2-input AND into 2nd input of 2-input NOR**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hd__a2bb2oi`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hd__a2bb2oi
-  **Library**: sky130_fd_sc_hd
-  **Inputs**:  4 (A1_N, A2_N, B1, B2)
-  **Outputs**: 1 (Y)

:cell:`sky130_fd_sc_hd__a2bb2oi` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_hd__a2bb2oi.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hd__a2bb2oi.pp.symbol.svg

:cell:`sky130_fd_sc_hd__a2bb2oi` schematic
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.. figure:: sky130_fd_sc_hd__a2bb2oi.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hd__a2bb2oi` GDSII layouts
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.. figure:: sky130_fd_sc_hd__a2bb2oi_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__a2bb2oi_1


.. figure:: sky130_fd_sc_hd__a2bb2oi_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__a2bb2oi_2


.. figure:: sky130_fd_sc_hd__a2bb2oi_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__a2bb2oi_4