:cell:`sky130_fd_io__top_sio_macro`
===================================

**sky130_fd_io__sio_macro consists of two SIO cells and a reference generator cell**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_io__top_sio_macro`
-  **Type**: cell
-  **Verilog name**: sky130_fd_io__top_sio_macro
-  **Library**: sky130_fd_io
-  **Inputs**:  21 (DFT_REFGEN, HLD_H_N_REFGEN, IBUF_SEL_REFGEN, ENABLE_VDDA_H, ENABLE_H, VOHREF, VREG_EN_REFGEN, VTRIP_SEL_REFGEN, SLOW, VTRIP_SEL, HLD_H_N, VREG_EN, VOH_SEL, INP_DIS, HLD_OVR, OE_N, VREF_SEL, IBUF_SEL, DM0, DM1, OUT)
-  **Outputs**: 3 (TIE_LO_ESD, IN_H, IN)

:cell:`sky130_fd_io__top_sio_macro` symbols
-------------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_io__top_sio_macro.symbol.svg
      -
      - .. figure:: sky130_fd_io__top_sio_macro.pp.symbol.svg

:cell:`sky130_fd_io__top_sio_macro` schematic
---------------------------------------------

.. figure:: sky130_fd_io__top_sio_macro.schematic.svg
    :align: center

:cell:`sky130_fd_io__top_sio_macro` GDSII layouts
-------------------------------------------------