SkyWater SKY130 PDK
SkyWater SKY130 PDK

Layers Reference

Layers Definitions

Table 16 Table C3: Device, LVS and other CAD definitions

Name

Defining algorithm

Used in …

AR_met2_A

Net Area Ratio of met2 not connected to via and of via2 >=0.05 [Equation: (AREA(via2))/(2 * AREA(met2NotConnVia) + PERIMETER(met2NotConnVia) * 0.35)]

Rules

AR_met2_B

Net Area Ratio of met2GroundOrFloat, via, and via2 <=0.032 [Equation: (AREA(via2))/(2 * AREA(met2GroundOrFloatVia) + PERIMETER(met2GroundOrFloatVia) * 0.35)]

Rules

bondPad

pad:dg OUTSIDE areaid:ft

Rules

bottom_plate

(capm:dg AND met2:dg) sized by capm.3; Exclude all capm sharing same metal2 plate

Rules

Capacitor

Capm enclosing at least one via2

Rules

Chip_extent

Holes (areaid:sl ) OR areaid.sl

Rules

Diecut_pmm

areaid.dt NOT (cfom.wp OR cp1m.wp OR cmm1.wp OR cmm2.wp)

Rules

drain_diffusion

(diff NOT poly in nwell or pwell) not abutting tap in the same well or abutting tap in the opposite well

Rules

dummy_capacitor

Capm not overlapping via2

Rules

dummy_poly

poly overlapping text “dummy_poly” (written using text.dg)

Rules

ESD_nwell_tap

n+ tap coincident with nwell such that n+ tap and nwell are completely surrounded by and abutting n+ diff on all edges, within areaid:ed

Rules

fomDmy_keepout_1

(diff.dg OR tap.dg OR poly.dg OR pwell resistor OR pad OR cfom.dg OR cfom.mk OR PhotoArray OR cp1m.mk)

Rules

floating_met*

met*.dg not connected to diffusion or tap through met(+1) or met(-1) and their respecitve vias and contacts

Rules

fom_waffles

fom.mk with dimensions (um x um): 0.5 x 0.5, 1.5 x 1.5, 2.5 x 2.5 and 4.08 x 4.08

Rules

gated_npn

cell name: s8rf_npn_1x1_2p0_HV

Rules

huge_metX

Metal X geometry wider and longer than 3.000um

Rules

hugePad

pad.mk with width > 100um

Rules

iso_pwell

(NOT nwell) AND dnwell

Rules

isolated_tap

tap that does not abut diff

Rules

laser_target

cell lazX_ and lazY_ OUTSIDE areaid:ft

Rules

LVnwell

nwell NOT hvi

Rules

LVTN_Gate

Gate overlapping lvtn

Rules

met2GroundOrFloat

met2 connected to ptap or met2 not connected to difftapn

Rules

met2GroundOrFloatVia

met2GroundOrFloat interacting with via2 >2

Rules

N+_diff

Diff NOT Nwell

Rules

N+_tap

Tap AND Nwell

Rules

nsdmHoles

Hole( nsdm )

Rules

NSM_keepout

nsm.dg OR nsm.mk

Rules

nwell_all

nwell OR extension of cnwm beyond nwell edge straddling de_nFet_source by cnwm.3f (45 degree edges are retained for the NVHV device nwell); Rule cnwm.3f applies only to GSMC flows

Rules

P+_diff

Diff AND Nwell

Rules

P+_tap

Tap NOT Nwell

Rules

Pattern_density

(diff_tap area) / PD window (as specified in the rule section)

Rules

photoDiode

deep nwell overlapping areaid.po. Die+frame utility will use the mask data of dnwell in the implementation of this definition

Rules

poly_licon1

Any licon1 that does not overlap ((diff or tap) NOT poly)

Rules

poly_waffles

p1m.mk with dimensions (um x um): 0.48 x 0.48, 0.54 x 0.54 and 0.72 x 0.72

Rules

prec_resistor

rpm AND (poly overlapping poly.rs) AND psdm

Rules

prec_resistor_terminal

prec_resistor AND li

Rules

psdmHoles

Hole( psdm )

Rules

pwell

NOT nwell (default substrate area)

Rules

pwres_terminal

P+tap abutting pwell.rs

Rules

pnp_emitter

diff AND pnp.dg AND psdm

Rules

routing_terminal

metX.pin sized inside of metX.drawing by 1/2 * metalX min width; Similar defintion applies to Li1 layer

Rules

scribe_line

areaid:ft NOT areaid:dt

Rules

slotted_licon

licon1.dg of size 0.19um x 2.0um

Rules

slotted_licon_edge1

2.0um edge of the slotted_licon

Rules

source_diffusion

(diff NOT poly in nwell or pwell) abutting tap in same well

Rules

tap_licon

Tap AND Licon1

Rules

tap_notPoly

tap NOT poly

Rules

top_indmMetal

met3 for S8D*

Rules

top_metal

met3.dg OR mm3.mk (for S8T*/SP8TEE-5R); met3.dg OR indm.mk (for S8D*); met4.dg OR mm4.mk (for SP8Q/S8Q*); met5.dg OR mm5.mk (for SP8P*/S8P*)

Rules

top_padVia

Via2 for S8D*

Rules

top_plate

capm:dg

Rules

Var_channel

poly AND tap AND (nwell NOT hvi) NOT areaid.ce

Rules

VaracTap

Tap overlapping Var_channel

Rules

vpp_with_noLi

vpp with cell names: FIXME

Rules

vpp_with_Met3Shield

vpp with cell names: FIXME

Rules

vpp_with_LiShield

vpp with cell names: FIXME

Rules

vpp_over_MOSCAP

vpp with cell names: FIXME when over nhvnative W/L=10x4, FIXME when over phv/pshort/phighvt/plowvt W/L=5x4

Rules

vpp_with_Met5PolyShield

vpp with cell names: FIXME

Rules

vpp_with_Met5

vpp with cell names: FIXME

Rules

cp1m_HV

cp1m AND Hvi

Rules (HV)

de_nFet_drain

((isolated tap) AND areaid.en) overlapping nwell

Rules (HV)

de_nFET_gate

deFET_gate overlapping (diff NOT dnwell)

Rules (HV)

de_nFet_source

(diff AND areaid.en) overlapping de_nFET_gate

Rules (HV)

de_pFet_drain

((isolated tap) AND areaid.en) not overlapping nwell

Rules (HV)

de_pFET_gate

deFET_gate overlapping (diff AND dnwell)

Rules (HV)

de_pFet_source

(diff AND areaid.en) overlapping de_pFET_gate

Rules (HV)

deFET_gate

(poly AND areaid.en) not overlapping pwm ; For CAD flows that do not have pwm layer, it is (poly AND areaid.en)

Rules (HV)

Hdiff

Diffusion AND Hvi

Rules (HV)

Hgate

Hpoly AND diff

Rules (HV)

Hnwell

Nwell AND Hvi

Rules (HV)

Hpoly

Poly AND Hvi

Rules (HV)

Htap

Tap AND Hvi

Rules (HV)

hv_source/drain

= (diff andNot poly) that overlaps diff.hv

Rules (HV)

hvFET_gate

= FET_gate butting hv_source/drain

Rules (HV)

hvPoly

= poly electrically connected to hv_source/drain

Rules (HV)

HV_nwell

(nwell AND hvi) OR (nwell overlapping areaid.hl)

Rules (HV)

stack_hv_lv_diff

(diff And Hvi NOT nwell) abutting (diff NOT nwell)

Rules (HV)

SHVdiff

Diff And shvi

Rules (SHV)

SHVGate

SHVPoly AND diff

Rules (SHV)

SHVPoly

Poly OVERLAP shvi:dg

Rules (SHV)

SHVSourceDrain

Diff And shvi NOT poly NOT diff:rs

Rules (SHV)

VHVdiff

Diff And vhvi

Rules (VHV)

VHVGate

VHVPoly AND diff

Rules (VHV)

VHVPoly

Poly OVERLAP vhvi:dg

Rules (VHV)

VHVSourceDrain

(Diff AND tap) And vhvi NOT poly NOT diff:rs

Rules (VHV)

background

Area where waffling grid is defined, sized to avoid waffle shift between runs

Waffles

die

Holes (areaid:sl )

Waffles

frame

( areaid.ft SIZE by -(max of s.2e/h)) NOT (OR areaid.dt SEALIDandHole)

Waffles

inductor_metal

(inductor:dg AND (met1 OR met2 OR met3)) size by 10 um [For all flows except S8PIR-10R]ninductor.dg [for the S8PIR-10R flow]

Waffles

mm*_slot

mm* slots are defined as empty holes in metal that are located in (areaid.cr OR areaid.cd)

Waffles

nwellDnwellHoles

(inner HOLES of nwellAndDnwell). Die+frame utility will use the mask data of nwell and dnwell in the implementation of this definition

Waffles

photoArray

(OR nwellAndDnwell nwellDnwellHoles) enclosing photoDiode. Die+frame utility will use the mask data of nwell and dnwell in the implementation of this definition

Waffles

gate

poly AND diff

pfet, nfet (LVS)

nfet

Gate NOT nwell

pfet, nfet (LVS)

pfet

Gate AND nwell

pfet, nfet (LVS)

nDiode

Ndiff AND DiodeID

Diodes (LVS)

Pdiff

diff AND nwell

Diodes (LVS)

pDiode

Pdiff AND DiodeID

Diodes (LVS)

diff_hole

Hole( diff )

ESD (LVS)

diff_tap_nwell

tap_nwell INSIDE diff_hole

ESD (LVS)

esd_diff_tap_nwell

ESDID AND diff_tap_nwell

ESD (LVS)

Ndiff

diff NOT nwell

ESD (LVS)

tap_nwell

tap INSIDE nwell

ESD (LVS)

ESD_diffusion

A+B31ny diffusion or ESD_nwell_tap connected directly or through a resistor to a Pad or to Vss/Vcc that is covered by areaid.ed and located within a double tap guardrings.

Latch up rules

ESD_cascode_diffusion

Diffusion covered by areaid.ed between two minimum spaced poly gates and located within a pair of double tap guardrings. (There should be no licons on the diffusion.)

Latch up rules

ESD_diode

Any nwell (other than ESD_nwell_tap ) covered by areaid.ed and areaid.de that does not contain poly

Latch up rules

ESD_FET

(any Pdiff covered by areaid:ed within a double tap guardrings) OrnESD_NFET

Latch up rules

ESD_NFET

(any Ndiff covered by areaid:ed abutting ESD_nwell_tap) Or (any Ndiff covered by areaid:ed abutting gate within 3.5um of ESD_nwell_tap) Or (any Ndiff abutting ESD_nwell_tap within areaid.ed) a double tap guardrings

Latch up rules

I/O_or_Output_Pmos

ESD P+ diffusion overlapping poly and overlapping ESD source/drain diffusion connected to I/O or output net

Latch up rules

I/O_Pmos_w/series_R

ESD PMOS connected to I/O or output net through series resistors

Latch up rules

met_ESD_resistor

Metal resistor inside areaid:ed

Latch up rules

Non_Vcc_nwell

Any nwell connected to any bias other than power supply

Latch up rules

Nwell_area

Is determined using the following steps:n(a) Grow pdiff by 1.5 mmn(b) Mergen(c) And Nwell:dg

Latch up rules

Pwell_area

Is determined using the following steps:n(a) Grow ndiff by 1.5 mmn(b) Mergen(c) NOT Nwell:dg

Latch up rules

Series_transistors

Merged diffusion determined by Nwell_area and Pwell_area

Latch up rules

fuse:dg

met2:fe for S8D*/S8TM*, met3.fe for S8TEE*/S8TNV/S8Q*/SP8TEE-5R/SP8Q*, met4.fe for S8P*/SP8P*

Fuse rules

fuse_contact

(fuse_metal overlapping fuse:dg) NOT fuse:dg

Fuse rules

fuse_metal

met3 for S8TEE*/S8TNV/S8Q*/SP8TEE-5R/SP8Q*; met2 for S8D*/S8TM*, met4 for S8P*/SP8P*

Fuse rules

fuse_shield

Metal line (same metal level as fuse) between fuse and periphery, not overlapping contacts or vias, with specified dimensions

Fuse rules

non-isolated fuse edge

Long edge of the fuse spaced to Met2/Met3/Met4 less than a specified amount

Fuse rules

single_fuses

Fuses without neighboring fuses within specified distance

Fuse rules

Auxiliary Layers

Table 17 Table C4a: Purpose layer description in LSW window and Auxiliary Layers

waffle_chip

icfb ver 5.0

icfb ver 5.1

drawing

dg

drw

pin

pn

pin

boundary

by

bnd

net

nt

net

res

rs

res

label

ll

lbl

cut

ct

cut

short

st

sho

pin

pn

pin

gate

ge

gat

probe

pe

pro

blockage

be

blo

model

ml

mod

optionX (X = 1…n)

oX (X = 1..n)

opt*(X=1..n)

fuse

fe

fus

mask

mk

mas*

maskAdd

md

mas*

maskDrop

mp

mas*

waffleAdd1

w1

waffleAdd1

waffleAdd2

w2

waffleAdd2

waffleDrop

wp

waf

error

er

err

warning

wg

wng

dummy

dy

dmy

Table 18 Table C4b: Purpose layer description in LSW window and Auxiliary Layers

waffle_chip

icfb ver 5.0

icfb ver 5.1

drawing

dg

drw

pin

pn

pin

boundary

by

bnd

net

nt

net

res

rs

res

label

ll

lbl

cut

ct

cut

short

st

sho

pin

pn

pin

gate

ge

gat

probe

pe

pro

blockage

be

blo

model

ml

mod

optionX (X = 1…n)

oX (X = 1..n)

opt*(X=1..n)

fuse

fe

fus

mask

mk

mas*

maskAdd

md

mas*

maskDrop

mp

mas*

waffleAdd1

w1

waffleAdd1

waffleAdd2

w2

waffleAdd2

waffleDrop

wp

waf

error

er

err

warning

wg

wng

dummy

dy

dmy

Layout Data Name & GDSII No.

Brief description

icfb ver 5.1

Identifiesn(See WOLF-41, SPR 95111 for more details)

Who

Use

areaid.sl{81:1}

areaid sealring

areaid.sea

The area of the Seal ring

Tech

areaid.ww{81:13}

areaid Waffle Window

areaid.waf

Used to prevent waffle shifting. When larger than areaid:sl re-defines the placement of waffles.

Frame

CLDRC

areaid.dn{81:50}

areaid dead Zon

areaid.dea

“deadzone” area in the DieSealR pcell (Seal Ring) for metal stress relief rule checks

Tech

areaid.cr{81:51}

areaid critCorner

areaid.cri*

For portions of layout that are not to be put in the critical side do to stress constraints. Should be used sparingly and only over the portion of the layout to remove DRC violations. Avoid using a blanket polygon over the entire layout. This layer is to be used instead of using the noCritSideReg verification option in Stress.n“critical corner” area in the DieSealR pcell (Seal Ring) for metal stress relief rule checks

Tech

Stress

areaid.cd{81:52}

areaid critSid

areaid.cri*

“criticalsid” area in the DieSealR pcell (Seal Ring) for metal stress relief rule checks

Tech

Stress

areaid.ce{81:2}

areaid core

areaid.cor

Memory core (memory cells and approved on-pitch only)

Tech

DRC

areaid.fe{81:3}

areaid frame

areaid.fra*

Pads in the frame

Frame

DRC

areaid.ed{81:19}

areaid ESD

areaid.esd

ESD devices- Surrounds any diffusion or ESD nwell tap connected to a signal pad. (only over ESD devices with special poly/tap exemption rules per LFL)

ESD, Des

DRC

areaid.dt{81:11}

areaid die cut

areaid.die

Location of the die within the frame used in frame builder ngeneration to create blanking for die and other drop-ins. Also used in cldrc/drc for rules in frame to die edge (waffles, nsm, metals etc)

Frame

Tech

areaid.mt{81:10}

areaid module cut

areaid.mod

Location of e-test modules within the frame used in frame builder generation to create data in scribe lane(example: opaque/clear masks) and to mark location of cells (etest and fab)for frame reports. Also used in drc/cldrc for rules to cell edge.

Frame

Tech

areaid.ft{81:12}

areaid frameRect

areaid.fra*

Boundary of the frame used in frame builder generation to mark boundary of frame. Also used in cldrc/drc for rules to frame edge

Frame

DRC/CLDRC

areaid.de{81:23}

areaid Diode

areaid.dio

The area occupied by diodes; Used to identify diodes during LVS

All

LVS

areaid.sc{81:4}

areaid standardc

areaid.sta

Cells in the standard cell library (over standard cell IP blocks only) .

Standard cell

DRC

areaid.st{81:53}

areaid SubstrateCut

areaid.sub

Regions to be considered as isolated substrates (only to designate 2 different resistively connected substrate nregions, >100um apart)

Tech, Des, ESD

Latch up, LVS, soft

areaid.en{81:57}

areaid extended drain

areaid.ext

Used to identify the extended drain devices

Tech, Des, ESD

LVS

areaid.le{81:60}

areaid LV Native

areaid.lvn

Used to identify the 3V Native NMOS versus 5V Native NMOS

Tech, Des

LVS

areaid.po{81:81}

areaid photo

areaid.pho

The areaid id is to identify the dnwell photo diode

Tech, Des

DRC

areaid.et{81:101}

areaid etest

areaid.ete

Used in etest modules

Frame

DRC

areaid.ld{81:14}

areaid low tap density

areaid.low

6um tap to diff rule will not be checked in this regionnDiffusion >6u from related tap, requiring >50u from sigPadDiff && sigPadMetNtr).nShould be used sparingly and only over the portion of the layout to remove DRC violations. This layer is not to be used if a tapping solution can be found. This layer can only be used if there is low risk for latchup. This layer will be reviewed during PDQC.

All

DRC

areaid.ns{81:15)

areaid not-crtical side

areaid .not

critSideReg stress rules will not be checked in this regionnCannot be placed in the critical side – uncommon, or where stress nerrors can’t be fixed)

All

DRC

areaid.ij{81:17}

areaid injection

areaid.inj

Identify all circuits that are susceptible to injection and ensure no signal-pad connected diffusion is within 100u.n“areaid.inj” encloses any circuitry deemed sensitive (by design team) to injected substrate areaid.inj encloses any PVT compliant circuitry

All

DRC

areaid.hl{81:63}

areaid.hvnwell

areaid.hvn

Identify nwell hooked to HV but containing FETs with thin oxide; nPotential difference across the FET terminals is LVnUsed over lv devices, operating in lv mode, placed in hv nwells, and should NOT have hvi

All

DRC

areaid.re{81:125}

areaid rf diode

areaid.rfd

Defines rf diodes that need to be extracted with series resistance (memo GCZ-124/125)

All

LVS

areaid.rd{81:24}

areaid.rdlprobepad

areaid.rdl

Ignore RDL keepouts when opening up PMM2

All

CLDRC

areaid.sf{81:6}

areaid sigPadDiff

Identify all srdrn diffusions and tap which are intended to be nconnected to signal pad (io Nets). Goes over diffusions connected to a signal pad - including through a poly resistor

All

LATCHUP

areaid.sl{81:7}

areaid.sigPadWell

Identify all nwells and pwells which are intended to be connected to signal pad (io Nets). Goes over wells with tap connected to a signal pad, including through a poly resistor

All

LATCHUP

areaid.sr{81:8}

areaid sigPadMetNtr

Identify all srcdrn, tap, and wells which are intended to be nmetallically connected to signal pad (io Nets) not through a resistor. nMust be used in unison with areaid.sigPadDifff or areaid.sigPadWell.nUsed with one of the above 2 areaids, nodes metallically nconnection to a sigPad (not through res)

All

LATCHUP

inductor:dg{82:24}

ID layer for inductor

Inductors

Tech, Des

DRC

t1,2,3 {82:26, 27, 28}

terminal labels for inductor

Labels required by inductor terminals to be recognized as device

Tech, Des

LVS

poly:ml {66:83}

poly device model

Model name extraction

Tech, Des, ESD

LVS

ncm {92:44}

N-Core Implant

Ncm.dg is available as a drawn layer

All

DRC/CLDRC

protect)

VPP capacitor

Interdigitated, vertical Li1, M1 and M2 capacitor

All

LVS

capm_2t.dg

MIM caps (2 terminal model)

ID layer for MIMCAP that will be treated as 2T device

All

DRC/LVS

cpmm:dg{91}

Drawn compatible polyimide layer

Drawn compatible layer and used only inside S8 RF pad

Frame

li1.be{67:10}

li1 blockage layer

Li1 blockage layer used for IP integration (per CWR 137)

All

DRC

met1.be{68:10}

Metal1 blockage layer

Metal 1 blockage layer used for IP integration (per CWR 137)

All

DRC

met2.be{69:10}

Metal2 blockage layer

Metal 2 blockage layer used for IP integration (per CWR 137)

All

DRC

met3.be{70:10}

Metal3 blockage layer

Metal 3 blockage layer used for IP integration (per CWR 137)

All

DRC

met4.be{71:10}

Metal4 blockage layer

Metal 4 blockage layer used for IP integration (per CWR 137)

All

DRC

met5.be{72:10}

Metal5 blockage layer

Metal 5 blockage layer used for IP integration (per CWR 137)

All

DRC

vhvi {74:21}

Very High voltage id layer

Used to identify nodes that operate at 12V nominal (16V max)

Des

VHV Rules

uhvi {74:22}

Ultra High voltage id layer

Used to identify nodes that operate at 20V nominal

Des

UHV Rules

areaid.e0{81:58}

Area extended drain

areaid.ext

Used to identify 20V drain extended devices

Des

LVS

areaid.zr{81:18}

Area zener diode

areaid.zen

Used to identify Zener diodes

Des

LVS

fom.dy{}

FOM dummy

FOM waffle drawn in this layer

All

Waffles

prune:dg{84:44}

prune

Areas ignored by LVS

Frame

LVS

areaid:cr {81:55}

copper pillar (.cuPillar)

areaid.cup

Placement of Cu pillar over the pad area, streamed out to Amkor, s8pfhd-10r flow only

Die

CLDRC s8pfhd-10r

cyprotect.dg {56.44}

External F25 layer

cyprotect.dg

Switch to direct streaming to drawn (no protect) or mask layer (with protect)

Frame

CLDRC

cytextmc.dg {50:44}

Locations for mask compose

cytextmc.dg

Text to extract placement for Fab25 tool

Frame

CLDRC

cypsbr.dg {51:44}

No phaseshift allowed

cypsbr.dg

Phaseshift layer common to all F25 phaseshift masks

Frame

areaid:ag{81:79}

analog

areaid.ana

Used to identify analog circuits

All

Analog

natfet.dg {124:21}

DEFETs

natfet.dg

Add TUNM for SONOS channel implants. See SPR 117559, SGL-529

All

DRC/CLDRC

areaid:lw

Ultra High voltage id layer

Areaid low voltage: UHV box to put all HV/LV curcuits in

All

Analog

  • To distinguish the layers, the full name of the layer needs to be turned on in the LSW window

As the layers are displayed in LSW window in icfb version 5.0; For purpose layer displayed in version 5.1, pls refer table C3

Devices and Layout vs Schematic (LVS) Information

Table 19 Table F2a: Devices and Layout vs. Schematic (LVS)

waffle_chip

icfb ver 5.0

icfb ver 5.1

drawing

dg

drw

pin

pn

pin

boundary

by

bnd

net

nt

net

res

rs

res

label

ll

lbl

cut

ct

cut

short

st

sho

pin

pn

pin

gate

ge

gat

probe

pe

pro

blockage

be

blo

model

ml

mod

optionX (X = 1…n)

oX (X = 1..n)

opt*(X=1..n)

fuse

fe

fus

mask

mk

mas*

maskAdd

md

mas*

maskDrop

mp

mas*

waffleAdd1

w1

waffleAdd1

waffleAdd2

w2

waffleAdd2

waffleDrop

wp

waf

error

er

err

warning

wg

wng

dummy

dy

dmy

Layout Data Name & GDSII No.

Brief description

icfb ver 5.1

Identifiesn(See WOLF-41, SPR 95111 for more details)

Who

Use

areaid.sl{81:1}

areaid sealring

areaid.sea

The area of the Seal ring

Tech

areaid.ww{81:13}

areaid Waffle Window

areaid.waf

Used to prevent waffle shifting. When larger than areaid:sl re-defines the placement of waffles.

Frame

CLDRC

areaid.dn{81:50}

areaid dead Zon

areaid.dea

“deadzone” area in the DieSealR pcell (Seal Ring) for metal stress relief rule checks

Tech

areaid.cr{81:51}

areaid critCorner

areaid.cri*

For portions of layout that are not to be put in the critical side do to stress constraints. Should be used sparingly and only over the portion of the layout to remove DRC violations. Avoid using a blanket polygon over the entire layout. This layer is to be used instead of using the noCritSideReg verification option in Stress.n“critical corner” area in the DieSealR pcell (Seal Ring) for metal stress relief rule checks

Tech

Stress

areaid.cd{81:52}

areaid critSid

areaid.cri*

“criticalsid” area in the DieSealR pcell (Seal Ring) for metal stress relief rule checks

Tech

Stress

areaid.ce{81:2}

areaid core

areaid.cor

Memory core (memory cells and approved on-pitch only)

Tech

DRC

areaid.fe{81:3}

areaid frame

areaid.fra*

Pads in the frame

Frame

DRC

areaid.ed{81:19}

areaid ESD

areaid.esd

ESD devices- Surrounds any diffusion or ESD nwell tap connected to a signal pad. (only over ESD devices with special poly/tap exemption rules per LFL)

ESD, Des

DRC

areaid.dt{81:11}

areaid die cut

areaid.die

Location of the die within the frame used in frame builder ngeneration to create blanking for die and other drop-ins. Also used in cldrc/drc for rules in frame to die edge (waffles, nsm, metals etc)

Frame

Tech

areaid.mt{81:10}

areaid module cut

areaid.mod

Location of e-test modules within the frame used in frame builder generation to create data in scribe lane(example: opaque/clear masks) and to mark location of cells (etest and fab)for frame reports. Also used in drc/cldrc for rules to cell edge.

Frame

Tech

areaid.ft{81:12}

areaid frameRect

areaid.fra*

Boundary of the frame used in frame builder generation to mark boundary of frame. Also used in cldrc/drc for rules to frame edge

Frame

DRC/CLDRC

areaid.de{81:23}

areaid Diode

areaid.dio

The area occupied by diodes; Used to identify diodes during LVS

All

LVS

areaid.sc{81:4}

areaid standardc

areaid.sta

Cells in the standard cell library (over standard cell IP blocks only) .

Standard cell

DRC

areaid.st{81:53}

areaid SubstrateCut

areaid.sub

Regions to be considered as isolated substrates (only to designate 2 different resistively connected substrate nregions, >100um apart)

Tech, Des, ESD

Latch up, LVS, soft

areaid.en{81:57}

areaid extended drain

areaid.ext

Used to identify the extended drain devices

Tech, Des, ESD

LVS

areaid.le{81:60}

areaid LV Native

areaid.lvn

Used to identify the 3V Native NMOS versus 5V Native NMOS

Tech, Des

LVS

areaid.po{81:81}

areaid photo

areaid.pho

The areaid id is to identify the dnwell photo diode

Tech, Des

DRC

areaid.et{81:101}

areaid etest

areaid.ete

Used in etest modules

Frame

DRC

areaid.ld{81:14}

areaid low tap density

areaid.low

6um tap to diff rule will not be checked in this regionnDiffusion >6u from related tap, requiring >50u from sigPadDiff && sigPadMetNtr).nShould be used sparingly and only over the portion of the layout to remove DRC violations. This layer is not to be used if a tapping solution can be found. This layer can only be used if there is low risk for latchup. This layer will be reviewed during PDQC.

All

DRC

areaid.ns{81:15)

areaid not-crtical side

areaid .not

critSideReg stress rules will not be checked in this regionnCannot be placed in the critical side – uncommon, or where stress nerrors can’t be fixed)

All

DRC

areaid.ij{81:17}

areaid injection

areaid.inj

Identify all circuits that are susceptible to injection and ensure no signal-pad connected diffusion is within 100u.n“areaid.inj” encloses any circuitry deemed sensitive (by design team) to injected substrate areaid.inj encloses any PVT compliant circuitry

All

DRC

areaid.hl{81:63}

areaid.hvnwell

areaid.hvn

Identify nwell hooked to HV but containing FETs with thin oxide; nPotential difference across the FET terminals is LVnUsed over lv devices, operating in lv mode, placed in hv nwells, and should NOT have hvi

All

DRC

areaid.re{81:125}

areaid rf diode

areaid.rfd

Defines rf diodes that need to be extracted with series resistance (memo GCZ-124/125)

All

LVS

areaid.rd{81:24}

areaid.rdlprobepad

areaid.rdl

Ignore RDL keepouts when opening up PMM2

All

CLDRC

areaid.sf{81:6}

areaid sigPadDiff

Identify all srdrn diffusions and tap which are intended to be nconnected to signal pad (io Nets). Goes over diffusions connected to a signal pad - including through a poly resistor

All

LATCHUP

areaid.sl{81:7}

areaid.sigPadWell

Identify all nwells and pwells which are intended to be connected to signal pad (io Nets). Goes over wells with tap connected to a signal pad, including through a poly resistor

All

LATCHUP

areaid.sr{81:8}

areaid sigPadMetNtr

Identify all srcdrn, tap, and wells which are intended to be nmetallically connected to signal pad (io Nets) not through a resistor. nMust be used in unison with areaid.sigPadDifff or areaid.sigPadWell.nUsed with one of the above 2 areaids, nodes metallically nconnection to a sigPad (not through res)

All

LATCHUP

inductor:dg{82:24}

ID layer for inductor

Inductors

Tech, Des

DRC

t1,2,3 {82:26, 27, 28}

terminal labels for inductor

Labels required by inductor terminals to be recognized as device

Tech, Des

LVS

poly:ml {66:83}

poly device model

Model name extraction

Tech, Des, ESD

LVS

ncm {92:44}

N-Core Implant

Ncm.dg is available as a drawn layer

All

DRC/CLDRC

protect)

VPP capacitor

Interdigitated, vertical Li1, M1 and M2 capacitor

All

LVS

capm_2t.dg

MIM caps (2 terminal model)

ID layer for MIMCAP that will be treated as 2T device

All

DRC/LVS

cpmm:dg{91}

Drawn compatible polyimide layer

Drawn compatible layer and used only inside S8 RF pad

Frame

li1.be{67:10}

li1 blockage layer

Li1 blockage layer used for IP integration (per CWR 137)

All

DRC

met1.be{68:10}

Metal1 blockage layer

Metal 1 blockage layer used for IP integration (per CWR 137)

All

DRC

met2.be{69:10}

Metal2 blockage layer

Metal 2 blockage layer used for IP integration (per CWR 137)

All

DRC

met3.be{70:10}

Metal3 blockage layer

Metal 3 blockage layer used for IP integration (per CWR 137)

All

DRC

met4.be{71:10}

Metal4 blockage layer

Metal 4 blockage layer used for IP integration (per CWR 137)

All

DRC

met5.be{72:10}

Metal5 blockage layer

Metal 5 blockage layer used for IP integration (per CWR 137)

All

DRC

vhvi {74:21}

Very High voltage id layer

Used to identify nodes that operate at 12V nominal (16V max)

Des

VHV Rules

uhvi {74:22}

Ultra High voltage id layer

Used to identify nodes that operate at 20V nominal

Des

UHV Rules

areaid.e0{81:58}

Area extended drain

areaid.ext

Used to identify 20V drain extended devices

Des

LVS

areaid.zr{81:18}

Area zener diode

areaid.zen

Used to identify Zener diodes

Des

LVS

fom.dy{}

FOM dummy

FOM waffle drawn in this layer

All

Waffles

prune:dg{84:44}

prune

Areas ignored by LVS

Frame

LVS

areaid:cr {81:55}

copper pillar (.cuPillar)

areaid.cup

Placement of Cu pillar over the pad area, streamed out to Amkor, s8pfhd-10r flow only

Die

CLDRC s8pfhd-10r

cyprotect.dg {56.44}

External F25 layer

cyprotect.dg

Switch to direct streaming to drawn (no protect) or mask layer (with protect)

Frame

CLDRC

cytextmc.dg {50:44}

Locations for mask compose

cytextmc.dg

Text to extract placement for Fab25 tool

Frame

CLDRC

cypsbr.dg {51:44}

No phaseshift allowed

cypsbr.dg

Phaseshift layer common to all F25 phaseshift masks

Frame

areaid:ag{81:79}

analog

areaid.ana

Used to identify analog circuits

All

Analog

natfet.dg {124:21}

DEFETs

natfet.dg

Add TUNM for SONOS channel implants. See SPR 117559, SGL-529

All

DRC/CLDRC

areaid:lw

Ultra High voltage id layer

Areaid low voltage: UHV box to put all HV/LV curcuits in

All

Analog

  • To distinguish the layers, the full name of the layer needs to be turned on in the LSW window

As the layers are displayed in LSW window in icfb version 5.0; For purpose layer displayed in version 5.1, pls refer table C3

Explanation of symbols:

  • - = Layer illegal for the device

  • + = Layer allowed to overlap

  • D = DRAWN indicates that a layer is drawn by Design.

  • C = CREATED indicates that the layer is only created by CAD.

Footnotes

1

Low vt needs to be set on the schematic element

2

Ncm is drawn inside core. Otherwise it is created in periphery. See rules ncm.X.* for details

3(1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19)

Drawn over half of device

4

ASSUMPTION: FET models will be same regardless of backend flow

5(1,2,3,4,5,6)

The 2 core FETs and flash npass must have a poly.ml label with their model name.

6(1,2,3,4,5,6,7)

over the drain

7(1,2,3,4,5,6,7)

over the source

8(1,2,3,4,5,6,7,8,9,10,11,12,13,14)

Information for RCX

9

Uses a black box for LVS. This is a fixed layout; Use symbol provided by modeling group

10

LVS will check that phighvt inside areaid.ce overlaps ncm

11(1,2,3)

The default model is sonos_e, sonos_de and nvssonos_e. If sonos_p, sonos_dp and nvssonos_p model are required, poly.ml must be used

12(1,2,3,4,5,6)

The capacitor.dg is drawn 0.17um from the edge of the cell to be LVS clean

13(1,2,3)

Devices are LVS’ed by cell name, m=1 per cell, fixed area and perimeter (see QHC-18)

14

(dnwell not (pwres or pnp or npn or areaid.en or areaid.de or areaid.po)) not nwell must have condiode text; Refer to VUN-104, 192 for condiode usage

15

Tech element is created by the user, no CAD supplied tech element

16(1,2,3)

There are multiple configurations of the Cu inductor. The layers present in one configuration may not be drawn in the other configuration. Also rdl will not be routed over met5 cu inductor, not checkable by CAD flow.

17(1,2,3,4)

Used for substrate noise isolation regions only

18(1,2)

Either UHVI or areaid.low_vt should be drawn over the sturctures

19(1,2)

Psub-Deep Nwell Diode must have condiode text “condiodeHvPsub”; CVA-596

20

mrp1 can’t overlay capacitor.dg: exempted s8rf2_xcmvpp11p5x11p7_lim5shield from the rule

Table 20 Table F2b: Mask Generation table

Category

Name

Used?

Layout Model and required schematic element

FOM

DNM

PWBM

PWDEM

NWM

HVTPM

LVTNM

NCM

TUNM

ONOM

LVOM

RPM

P1M

HVNTM

NTM

LDNTM

NPC

NSDM

PSDM

LICM1

LI1M

CAPM

MM1

MM2

MM3

MM5

CU1M

INDM

Drawn Route / Comments

RESISTOR

n diff resistor

res r

sky130_fd_pr__res_generic_nd

C

C

RESISTOR

HV n diff resistor

res r

mrdn_hv

C

C

C

C

C

RESISTOR

p diff resistor

res r

sky130_fd_pr__res_generic_pd

C

C

C

C

C

C

RESISTOR

p diff resistor NV

res r

sky130_fd_pr__res_generic_pd

C

C

C

C

C

C

RESISTOR

HV p diff resistor

res r

mrdp_hv

C

C

C

C

C

RESISTOR

Isolated Pwell resistor

respw

sky130_fd_pr__res_iso_pw

C

C

RESISTOR

n+ poly resistor

res

sky130_fd_pr__res_generic_po

C

RESISTOR

p+ poly resistor

res3

xhrpoly_*_*

C

C

C

C

C

RESISTOR

li resistor

res

sky130_fd_pr__res_generic_l1

C

RESISTOR

metal fuse_D

mrmX

mrmX

C

metX AND metX.fe

RESISTOR

metal fuse_T

mrmX

mrmX

C

metX AND metX.fe

32 A CMOS

nmos 1.8V

nfet

sky130_fd_pr__nfet_01v8

C

C

C

32 A CMOS

pmos 1.8V

pfet

sky130_fd_pr__pfet_01v8

C

C

C

C

C

C

C

32 A CMOS

pmos 1.8V NV

pfet

sky130_fd_pr__pfet_01v8

C

C

C

C

C

C

C

32 A CMOS

Low Vt pmos 1.8V 32A

pfet

sky130_fd_pr__pfet_01v8_lvt

C

C

C

C

C

C

32 A CMOS

High Vt pmos 1.8V 32A

pfet

sky130_fd_pr__pfet_01v8_hvt

C

C

C

C

C

C

C

C

32 A CMOS

High Vt pmos 1.8V 32A NV

pfet

sky130_fd_pr__pfet_01v8_hvt

C

C

C

C

C

C

C

C

32 A CMOS

Low Vt nmos 1.8V 32A

nfet

sky130_fd_pr__nfet_01v8_lvt

C

C

C

C

32 A CMOS

nmos_core

nfet

sky130_fd_pr__special_nfet_pass

C

C

C

32 A CMOS

nmos_core

nfet

sky130_fd_pr__special_nfet_latch

C

C

C

32 A CMOS

nmos_core NV

nfet

sky130_fd_pr__special_nfet_pass_lowleakage

C

C

C

C

C

32 A CMOS

nmos_core NV

nfet

sky130_fd_pr__special_nfet_latch_lowleakage

C

C

C

C

C

32 A CMOS

pmos_core

pfet

sky130_fd_pr__special_pfet_pass

C

C

C

C

C

C

C

C

32 A CMOS

pmos_core NV

pfet

sky130_fd_pr__special_pfet_pass_lowleakage

C

C

C

C

C

C

C

32 A CMOS

Low Vt nmos_core

C

C

C

C

32 A CMOS

Low Vt Varactor

capbn

sky130_fd_pr__cap_var_lvt

C

C

C

C

C

C

32 A CMOS

High Vt Varactor

capbn

sky130_fd_pr__cap_var_hvt

C

C

C

C

C

C

C

C

32 A CMOS

HV varactor (floating gate)

C

C

C

C

C

C

C

C

C

SONOS (& SONOS Latch)

SONOS fet

nfet

sky130_fd_bs_flash__special_sonosfet_original

C

C

C

C

C

C

C

C

C

C

SONOS (& SONOS Latch)

SONOS fet

nfet

sky130_fd_bs_flash__special_sonosfet_star

C

C

C

C

C

C

C

C

C

C

SONOS (& SONOS Latch)

NV SONOS fet

nfet

nvssonos_p

C

C

C

C

C

C

C

C

C

SONOS (& SONOS Latch)

NV SONOS fet

nfet

nvssonos_e

C

C

C

C

C

C

C

C

C

110A CMOS

HV nmos 5/10.5V

nfet

sky130_fd_pr__nfet_g5v0d10v5

C

C

C

C

C

C

110A CMOS

HV pmos 5/10.5 V

pfet

sky130_fd_pr__pfet_g5v0d10v5

C

C

C

C

C

C

110A CMOS

Native nmos 5V

nfet

sky130_fd_pr__nfet_05v0_nvt

C

C

C

C

C

C

C

110A CMOS

Native nmos 3V

nfet

sky130_fd_pr__nfet_03v3_nvt

C

C

C

C

C

C

C

110A CMOS

Flash npass

nfet

sky130_fd_pr__special_nfet_pass_flash

C

C

C

C

C

C

110A CMOS

Flash npass NV

nfet

nvsrnpass

C

C

C

C

C

C

110A CMOS

VHV nmos 5/16V DE

nfet

sky130_fd_pr__nfet_g5v0d16v0

C

C

C

C

C

C

C

110A CMOS

VHV pmos 5/16V DE

pfet

sky130_fd_pr__pfet_g5v0d16v0

C

C

C

C

C

C

C

110A CMOS

UHV nmos 5/20V DE

nfete

C

C

C

C

C

C

C

C

110A CMOS

UHV iso nmos 5/20V DE

nfete

C

C

C

C

C

C

C

C

110A CMOS

UHV Native nmos 5/20V DE

TBA

C

C

C

C

C

C

C

C

110A CMOS

UHV Native iso nmos 5/20V DE

nfete

C

C

C

C

C

C

C

C

110A CMOS

UHV pmos 5/20V DE

pfete

C

C

C

C

C

C

C

C

C

CAPACITOR

MiM

cmim3

sky130_fd_pr__model__cap_mim

C

C

CAPACITOR

VPP

cap

sky130_fd_pr__cap_vpp_XXXXXX

C

C

C

CAPACITOR

VPP (with met3 shield)

vppca

C

C

C

C

INDUCTOR

Inductor

induc

sky130_fd_pr__ind

C

INDUCTOR

Cu Inductor

induc

sky130_fd_pr__ind

C

C

INDUCTOR

Balun Inductor

induc

sky130_fd_pr__ind

C

C

DIODE

nDiode

lvsdi

sky130_fd_pr__diode_pw2nd_05v5

C

C

DIODE

HV nDiode

lvsdi

sky130_fd_pr__diode_pw2nd_11v0

C

C

C

C

C

DIODE

RF ESD HV nDiode

lvsdi

sky130_fd_pr__diode_pw2nd_11v0

C

C

C

C

C

DIODE

RF ESD Deep Nwell nDiode

lvsdi

C

C

C

C

C

C

DIODE

pDiode

lvsdi

sky130_fd_pr__diode_pd2nw_05v5

C

C

C

C

C

C

DIODE

pDiode NV

lvsdi

sky130_fd_pr__diode_pd2nw_05v5

C

C

C

C

C

C

DIODE

HV pDiode

lvsdi

sky130_fd_pr__diode_pd2nw_11v0

C

C

C

C

C

DIODE

RF ESD HV pDiode

lvsdi

sky130_fd_pr__diode_pd2nw_11v0

C

C

C

C

C

DIODE

Photo Diode

lvsdi

dnwdiode

C

C

C

C

C

C

C

DIODE

Low Vt pdiode 21

diode

sky130_fd_pr__diode_pd2nw_05v5_lvt

C

C

C

C

C

DIODE

High Vt pDiode 21

diode

sky130_fd_pr__diode_pd2nw_05v5_hvt

C

C

C

C

C

C

C

DIODE

High Vt pDiode NV 21

diode

sky130_fd_pr__diode_pd2nw_05v5_hvt

C

C

C

C

C

C

C

DIODE

Low Vt nDiode 21

diode

sky130_fd_pr__diode_pw2nd_05v5_lvt

C

C

C

DIODE

NV SONOS Diode 21

diode

ndiode_nvs

C

C

C

C

C

C

DIODE

Native nDiode 21

diode

sky130_fd_pr__diode_pw2nd_05v5_nvt

C

C

C

C

C

DIODE

Nwell Diode 21

diode

sky130_fd_pr__model__parasitic__diode_ps2nw

C

DIODE

RF Nwell Diode 21

diode

sky130_fd_pr__model__parasitic__diode_ps2nw

C

DIODE

Pwell-Deep Nwell Diode 21

diode

sky130_fd_pr__model__parasitic__diode_pw2dn

C

DIODE

RF ESD Pwell-Deep Nwell Diode 21

diode

sky130_fd_pr__model__parasitic__diode_pw2dn

C

DIODE

RF Pwell-Deep Nwell Diode 21

diode

sky130_fd_pr__model__parasitic__diode_pw2dn

C

DIODE

Psub-Deep Nwell Diode 21

diode

sky130_fd_pr__model__parasitic__diode_ps2dn

C

DIODE

Psub-Deep Nwell Diode 21

diode

sky130_fd_pr__model__parasitic__diode_ps2dn

C

C

DIODE

HV Pwell-Deep Nwell Diode 21

diode

dnwdiode_hvpw

C

PNP

Parasitic PNP

pnp4

sky130_fd_pr__pnp_05v5_W0p68L0p68

C

C

C

C

C

C

C

Layout provided by technology

PNP

Parasitic NPN

pnp4

sky130_fd_pr__npn_05v5

C

C

C

C

C

Layout provided by technology

ESD transistor

LV nESD transistor

nfet

sky130_fd_pr__esd_nfet_01v8

C

C

C

NMOS with ESD_nwell_tap

ESD transistor

HV nESD transistor

nfet

sky130_fd_pr__esd_nfet_g5v0d10v5

C

C

C

C

C

C

NMOS with ESD_nwell_tap

ESD transistor

HV Native nESD transistor

C

C

C

C

C

C

C

ESD transistor

HV pESD transistor

pfet

sky130_fd_pr__esd_pfet_g5v0d10v5

C

C

C

C

C

C

Explanation of symbols:

  • - = Layer not created for the device

  • + = Layer allowed to overlap

  • C = CREATED

  • nr = next revision

Footnotes

21(1,2,3,4,5,6,7,8,9,10,11,12,13,14)

For RCX information

GDS Layers Information

The gds_layers.csv file provides a raw list of the layers used in the process with name, description and the GDS layer and data type.

Table 21 Table - GDS Layers

Layer name

Purpose

GDS layer:datatype

Description

diff

drawing, text

65:20

Active (diffusion) area (type opposite of well/substrate underneath)

tap

drawing

65:44

Active (diffusion) area (type equal to the well/substrate underneath) (i.e., N+ and P+)

nwell

drawing

64:20

N-well region

dnwell

drawing

64:18

Deep n-well region

pwbm

drawing

19:44

Regions (in UHVI) blocked from p-well implant (DE MOS devices only)

pwde

drawing

124:20

Regions to receive p-well drain-extended implants

hvtr

drawing

18:20

High-Vt RF transistor implant

hvtp

drawing

78:44

High-Vt LVPMOS implant

ldntm

drawing

11:44

N-tip implant on SONOS devices

hvi

drawing

75:20

High voltage (5.0V) thick oxide gate regions

tunm

drawing

80:20

SONOS device tunnel implant

lvtn

drawing

125:44

Low-Vt NMOS device

poly

drawing, text

66:20

Polysilicon

hvntm

drawing

125:20

High voltage N-tip implant

nsdm

drawing

93:44

N+ source/drain implant

psdm

drawing

94:20

P+ source/drain implant

rpm

drawing

86:20

300 ohms/square polysilicon resistor implant

urpm

drawing

79:20

2000 ohms/square polysilicon resistor implant

npc

drawing

95:20

Nitride poly cut (under licon1 areas)

licon1

drawing

66:44

Contact to local interconnect

li1

drawing, text

67:20

Local interconnect

mcon

drawing

67:44

Contact from local interconnect to metal1

met1

drawing, text

68:20

Metal 1

via

drawing

68:44

Contact from metal 1 to metal 2

met2

drawing, text

69:20

Metal 2

via2

drawing

69:44

Contact from metal 2 to metal 3

met3

drawing, text

70:20

Metal 3

via3

drawing

70:44

Contact from metal 3 to metal 4

met4

drawing, text

71:20

Metal 4

via4

drawing

71:44

Contact from metal 4 to metal 5

met5

drawing, text

72:20

Metal 5

pad

drawing, text

76:20

Passivation cut (opening over pads)

nsm

drawing

61:20

Nitride seal mask

capm

drawing

89:44

MiM capacitor plate over metal 3

cap2m

drawing

97:44

MiM capacitor plate over metal 4

vhvi

drawing

74:21

12V nominal (16V max) node identifier

uhvi

drawing

74:22

20V nominal node identifier

npn

drawing

82:20

Base region identifier for NPN devices

inductor

drawing

82:24

Identifier for inductor regions

capacitor

drawing

82:64

Identifier for interdigitated (vertical parallel plate (vpp)) capacitors

pnp

drawing

82:44

Base nwell region identifier for PNP devices

LVS prune

drawing

84:44

Exemption from LVS check (used in e-test modules only)

ncm

drawing

92:44

N-core implant

padCenter

drawing

81:20

Pad center marker

target

drawing

76:44

Metal fuse target

areaid.sl

identifier

81:1

Seal ring identifier

areaid.ce

identifier

81:2

Memory (SRAM) core cell identifier

areaid.fe

identifier

81:3

Pads in padframe identifier

areaid.sc

identifier

81:4

Standard cell identifier

areaid.sf

identifier

81:6

Signal pad diffusion identifier (for latchup DRC checks)

areaid.sl

identifier

81:7

Signal pad well identifier (for latchup DRC checks)

areaid.sr

identifier

81:8

Signal pad metal (for latchup DRC checks)

areaid.mt

identifier

81:10

Location of e-test modules within the frame

areaid.dt

identifier

81:11

Location of dice within the frame

areaid.ft

identifier

81:12

Boundary of the frame

areaid.ww

identifier

81:13

Waffle window (used to prevent waffle shifting)

areaid.ld

identifier

81:14

Low tap density (15um between taps) area. Must be at least 50um from padframe

areaid.ns

identifier

81:15

Non-critical side. Blocks stress DRC rules

areaid.ij

identifier

81:17

Identification for areas susceptible to injection

areaid.zr

identifier

81:18

Zener diode identifier

areaid.ed

identifier

81:19

ESD device identifier

areaid.de

identifier

81:23

Diode identifier

areaid.rd

identifier

81:24

RDL probe pad (not used in this process)

areaid.dn

identifier

81:50

Dead zone (used in seal ring only for stress DRC)

areaid.cr

identifier

81:51

Critical corner (used in seal ring only for stress DRC)

areaid.cd

identifier

81:52

Critical side (used in seal ring only for stress DRC)

areaid.st

identifier

81:53

Substrate cut. Idendifies areas to be considered as isolated substrate

areaid.op

identifier

81:54

OPC drop. Block automatic OPC (for fab blocks and lithocal structures)

areaid.en

identifier

81:57

Extended drain identifier

areaid.en20

identifier

81:58

20V Extended drain identifier

areaid.le

identifier

81:60

3.3V native NMOS identifier (absence indicates a 5V native NMOS)

areaid.hl

identifier

81:63

HV nwell. Identifies nwells with thin oxide devices connected to high voltage

areaid.sd

identifier

81:70

subcircuit identifier (for LVS extraction)

areaid.po

identifier

81:81

Photodiode device identifier

areaid.it

identifier

81:84

IP exempt from DFM rules

areaid.et

identifier

81:101

e-test module identifier

areaid.lvt

identifier

81:108

Low-Vt identifier

areaid.re

identifier

81:125

RF diode identifier

fom

dummy

22:23

poly

gate

66:9

poly

model

66:83

(Text type)

poly

resistor

66:13

diff

resistor

65:13

pwell

resistor

64:13

li1

resistor

67:13

diff

high voltage

65:8

met4

fuse

71:17

inductor

terminal1

82:26

inductor

terminal2

82:27

inductor

terminal3

82:28

li1

block

67:10

met1

block

68:10

met2

block

69:10

met3

block

70:10

met4

block

71:10

met5

block

72:10

prBndry

boundary

235:4

diff

boundary

65:4

tap

boundary

65:60

mcon

boundary

67:60

poly

boundary

66:4

via

boundary

68:60

via2

boundary

69:60

via3

boundary

70:60

via4

boundary

71:60

li1

label

67:5

(Text type)

met1

label

68:5

(Text type)

met2

label

69:5

(Text type)

met3

label

70:5

(Text type)

met4

label

71:5

(Text type)

met5

label

72:5

(Text type)

poly

label

66:5

(Text type)

diff

label

65:6

(Text type)

pwell

label

64:59

(Text and data type)

pwelliso

label

44:5

(Text type)

pad

label

76:5

(Text type)

tap

label

65:5

nwell

label

64:5

inductor

label

82:25

text

label

83:44

(Text type)

li1

net

67:23

(Text type)

met1

net

68:23

(Text type)

met2

net

69:23

(Text type)

met3

net

70:23

(Text type)

met4

net

71:23

(Text type)

met5

net

72:23

(Text type)

poly

net

66:23

(Text type)

diff

net

65:23

(Text type)

li1

pin

67:16

(Text and data)

met1

pin

68:16

(Text and data)

met2

pin

69:16

(Text and data)

met3

pin

70:16

(Text and data)

met4

pin

71:16

(Text and data)

met5

pin

72:16

(Text and data)

poly

pin

66:16

(Text and data)

diff

pin

65:16

(Text and data)

nwell

pin

64:16

(Text type)

pad

pin

76:16

(Text and data)

pwell

pin

122:16

(Text and data)

pwelliso

pin

44:16

(Text and data)

nwell

pin

64:0

(Text type)

poly

pin

66:0

(Text type)

li1

pin

67:0

(Text type)

met1

pin

68:0

(Text type)

met2

pin

69:0

(Text type)

met3

pin

70:0

(Text type)

met4

pin

71:0

(Text type)

met5

pin

72:0

(Text type)

pad

pin

76:0

(Text type)

pwell

pin

122:0

(Text type)

diff

cut

65:14

poly

cut

66:14

li1

cut

67:14

met1

cut

68:14

met2

cut

69:14

met3

cut

70:14

met4

cut

71:14

met5

cut

72:14

pwell

cut

met5

probe

72:25

met4

probe

71:25

met3

probe

70:25

met2

probe

69:25

met1

probe

68:25

li1

probe

67:25

poly

probe

66:25

poly

short

66:15

li1

short

67:15

met1

short

68:15

met2

short

69:15

met3

short

70:15

met4

short

71:15

met5

short

72:15

Mask level data

cncm

mask

17:0

N-core implant mask

crpm

mask

96:0

Resistor Protect mask

cpdm

mask

37:0

Pad mask

cnsm

mask

22:0

Nitride seal mask

cmm5

mask

59:0

Metal 5 mask

cviam4

mask

58:0

Via 4 mask

cmm4

mask

51:0

Metal 4 mask

cviam3

mask

50:0

Via 3 mask

cmm3

mask

34:0

Metal 3 mask

cviam2

mask

44:0

Via 2 mask

cmm2

mask

41:0

Metal 2 mask

cviam

mask

40:0

Via mask

cmm1

mask

36:0

Metal 1 mask

ctm1

mask

35:0

Contact mask

cli1m

mask

56:0

Local interconnect mask

clicm1

mask

43:0

Local interconnect contact mask

cpsdm

mask

32:0

P+ Implant mask

cnsdm

mask

30:0

N+ Implant mask

cldntm

mask

11:0

Lightly-doped N-tip implant mask

cnpc

mask

49:0

Nitride poly cut mask

chvntm

mask

39:0

High voltage N-tip implant mask

cntm

mask

27:0

N-tip implant mask

cp1m

mask

28:0

Poly 1 mask

clvom

mask

46:0

Low Voltage oxide mask

conom

mask

88:0

ONO Mask

ctunm

mask

20:0

Tunnel mask

chvtrm

mask

98:0

HLow VT PCh Radio mask

chvtpm

mask

97:0

High Vt Pch mask

clvtnm

mask

25:0

Low Vt Nch mask

cnwm

mask

21:0

Nwell mask

cdnm

mask

48:0

Deep nwell mask

cfom

mask

23:0

Field oxide mask

cfom

drawing

22:20

clvtnm

drawing

25:44

chvtpm

drawing

88:44

conom

drawing

87:44

clvom

drawing

45:20

cntm

drawing

26:20

chvntm

drawing

38:20

cnpc

drawing

44:20

cnsdm

drawing

29:20

cpsdm

drawing

31:20

cli1m

drawing

115:44

cviam3

drawing

112:20

cviam4

drawing

117:20

cncm

drawing

96:44

cntm

mask add

26:21

clvtnm

mask add

25:43

chvtpm

mask add

97:43

cli1m

mask add

115:43

clicm1

mask add

106:43

cpsdm

mask add

31:21

cnsdm

mask add

29:21

cp1m

mask add

33:43

cfom

mask add

22:21

cntm

mask drop

26:22

clvtnm

mask drop

25:42

chvtpm

mask drop

97:42

cli1m

mask drop

115:42

clicm1

mask drop

106:42

cpsdm

mask drop

31:22

cnsdm

mask drop

29:22

cp1m

mask drop

33:42

cfom

mask drop

22:22

cmm4

waffle drop

112:4

cmm3

waffle drop

107:24

cmm2

waffle drop

105:52

cmm1

waffle drop

62:24

cp1m

waffle drop

33:24

cfom

waffle drop

22:24

cmm5

waffle drop

117:4

Device and Layout vs. Schematic

Table 22 Table F2a: Devices and Layout vs. Schematic (LVS)

Category

Name

Used?

Required schematic elements

diff.dg

diff.rs

diff.ct

cfom.wp

tap.dg

dnwell:dg

pwbm.dg

pwdem:dg

hvtr.dg

nwell.dg

hvtp:dg

lvtn:dg

pwell.rs

pwell.ct

ncm.dg 2

tunm:dg

hvi:dg

rpm:dg

poly.dg

poly.rs

poly.ct

poly:ml

ldntm:dg

npc:dg

nsdm.dg

psdm.dg

licon.dg

li1.dg

li.rs

li.ct

capm:dg

capm_2t.dg

metX.dg

metX.fe

met1:dg

met2:dg

met3:dg

met4.dg

met5.dg

rdl.dg

inductor:dg

capacitor.dg

areaid.le

areaid.en

pnp.dg

npn.dg

areaid.st

areaid.de

areaid.re

areaid.po

areaid:ce

areaid.ed

areaid.ext

UHVI

areaid.low_vt

Drawn Route / Comments

Layout Model

RESISTOR

n diff resistor

X

res resn

D

D

D

D

mrdn

RESISTOR

HV n diff resistor

X

res resnhv

D

D

D

D

D

mrdn_hv

RESISTOR

p diff resistor

X

res resp

D

D

D

D

C

D

mrdp

RESISTOR

p diff resistor NV

res resp

D

D

D

D

C

D

mrdp

RESISTOR

HV p diff resistor

X

res resphv

D

D

D

D

D

D

mrdp_hv

RESISTOR

Isolated Pwell resistor

X

respw

D

D

D

D

xpwres

RESISTOR

n+ poly resistor

X

res

D

D

D

mrp1

RESISTOR

p+ poly resistor

X

res3

D

D

D

D

D

D

xhrpoly_*

RESISTOR

li resistor

X

res

D

D

D

mrl1

RESISTOR

metal fuse

X

mrmX

D

D

metX AND metX.fe

mrmX

32 A CMOS

nmos 1.8V

X

nfet

D

D

D

nshort

32 A CMOS

pmos 1.8V

X

pfet

D

D

C

C

D

D

pshort

32 A CMOS

Low Vt pmos 1.8V 32A

X

pfet

D

D

D

D

D

plowvt

32 A CMOS

High Vt pmos 1.8V 32A 10

X

pfet

D

D

D

C

D

D

phighvt

32 A CMOS

Low Vt nmos 1.8V 32A

X

nfet

D

D

D

D

nlowvt

32 A CMOS

nmos_core 5

X

nfet

D

D

D

D

D

npass npd

32 A CMOS

nmos_core NV 5

nfet

D

D

D

D

D

D

D

npassll npdll

32 A CMOS

pmos_core 5

X

pfet

D

D

D

C

D

D

D

D

D

ppu

32 A CMOS

pmos_core NV 5

pfet

D

D

D

C

D

D

D

D

ppull

32 A CMOS

Low Vt nmos_core 5

X

nfet

D

D

D

D

D

D

nlvtpass

32 A CMOS

Low Vt Varactor

X

capbn_b

D

D

C

D

D

xcnwvc

32 A CMOS

High Vt Varactor

X

capbn_b

D

D

D

C

C

D

D

xcnwvc2

32 A CMOS

HV varactor (floating gate)

X

capbn_b

D

D

D

D

D

D

xchvnwc

SONOS (& SONOS Latch)

SONOS fet 11

X

nfet

D

D

D

D

D

D

D

D

sonos_p/e

SONOS (& SONOS Latch)

SONOS fet 11

nfet

D

D

D

D

D

D

D

D

sonos_de/dp

SONOS (& SONOS Latch)

NV SONOS fet 11

nfet

D

D

D

D

D

D

D

D

nvssonos_p/e

110A CMOS

HV nmos 5/10.5V

X

nfet

D

D

D

D

nhv

110A CMOS

HV nmos 5/10.5V

nfet

D

D

D

D

D

nhvcore

110A CMOS

HV pmos 5/10.5V

X

pfet

D

D

D

D

D

phv

110A CMOS

HV pmos 5/10.5V

pfet

D

D

D

D

D

D

phvcore

110A CMOS

Native nmos 5V

X

nfet

D

D

D

D

D

nhvnative

110A CMOS

Native nmos 3V

X

nfet

D

D

D

D

D

D

ntvnative

110A CMOS

Flash npass 5

X

nfet

D

D

D

D

D

D

D

fnpass

110A CMOS

Flash npass NV

nfet

D

D

D

D

D

D 3

D

nvsrnpass

110A CMOS

VHV nmos 5/16V DE

X

nfetextd

D 7

D 6

D

D

D

D

D

nvhv

110A CMOS

VHV pmos 5/16V DE

X

pfetextd

D 7

D 6

D

D 3

D

D

D

D

pvhv

110A CMOS

UHV nmos 5/20V DE

nfetextd

D 7

D 6

D 3

D 3

D 3

D 3

D

D

D

D

D

D

n20vhv1

110A CMOS

UHV iso nmos 5/20V DE

nfetextdiso

D 7

D 6

D 3

D 3

D 3

D 3

D

D

D

D

D

D

n20vhviso1

110A CMOS

UHV Native nmos 5/20V DE

nfetextd

D 7

D 6

D 3

D 3

D 3

D

D

D

D

D

D

D

n20nativevhv1

110A CMOS

UHV Zvt nmos 5/20V DE

nfetextd

D 7

D 6

D 3

D

D 3

D

D

D

D

D

D

D

n20zvtvhv1

110A CMOS

UHV pmos 5/20V DE

pfetextd

D 7

D 6

D

D 3

D 3

D 3

D 3

D

D

D

D

D

D

p20vhv1

CAPACITOR

MiM (3 Terminal)

cmim3c

D

D

xcmimc

CAPACITOR

MiM (2 Terminal)

cmimc

D

D

D

xcmimc2

CAPACITOR

VPP 9

X

D

D

D

D

xcmvpp xcmvpp_2

CAPACITOR

VPP over NHVNATIVE

X

cap_int3

D

D

D

D

xcmvpp2_nhvnative10x4

CAPACITOR

VPP over PHV

X

cap_int3

D

D

D

D

xcmvpp2_phv5x4

CAPACITOR

VPP and NHVNATIVE

X

vppcap

D

D

D

D

D

xcmvppx4_2xnhvnative10x4

CAPACITOR

4-Terminal VPP (with Met3 shield) 12

X

vppcap

D

D

D

D

D

xcmvpp1p8x1p8_m3shield xcmvpp8p6x7p9_m3shield xcmvpp4p4x4p6_m3shield xcmvpp11p5x11p7_m3shield

CAPACITOR

4-terminal VPP (with M5 shield) 12

X

vppcap

D

D

D

D

D

D

D

xcmvpp11p5x11p7_m5shield xcmvpp11p5x11p7_polym5shield xcmvpp11p5x11p7_lim5shield xcmvpp8p6x7p9_m3_lim5shield xcmvpp11p5x11p7_m3_lim5shield xcmvpp4p4x4p6_m3_lim5shield xcmvpp11p5x11p7_m1m4m5shield xcmvpp11p5x11p7_polym50p4shield

CAPACITOR

4-terminal VPP (with M4 shield) 12

X

vppcap

D

D

D

D

D

D

xcmvpp11p5x11p7_m4shield xcmvpp11p5x11p7_polym4shield xcmvpp6p8x6p1_polym4shield xcmvpp6p8x6p1_lim4shield

CAPACITOR

3-Terminal VPP 12

X

cap_int3

D

D

D

D

xcmvpp1p8x1p8 xcmvpp3 xcmvpp4 xcmvpp5 xcmvpp4p4x4p6_m1m2 xcmvpp11p5x11p7_m1m2

CAPACITOR

3-Terminal VPP 12 (for S8Q/S8P ONLY)

X

cap_int3

D

D

D

D

D

xcmvpp8p6x7p9_m3_lishield xcmvpp4p4x4p6_m3_lishield xcmvpp11p5x11p7_m3_lishield

CAPACITOR

3-Terminal VPP 12 (for S8P ONLY)

X

cap_int3

D

D

D

D

D

D

xcmvpp11p5xx11p7_m1m4 xcmvpp_hd5_*

INDUCTOR

Inductor

inductor

D

D

xind

INDUCTOR

Cu Inductor

X

ind4

D

D 16

D 16

D

D 16

D

xind4

INDUCTOR

Balun Inductor 15

X

D

D

D

D

balun

DIODE

nDiode

X

lvsdiode

D

D

D

ndiode

DIODE

HV nDiode

X

lvsdiode

D

D

D

D

ndiode_h

DIODE

RF ESD HV nDiode 13

X

lvsdiode

D

D

D

D

D

xesd_ndiode_h_X (where X=100 200 300)

DIODE

RF ESD HV Deep Nwell nDiode 13

X

lvsdiode

D

D

D

D

D

D

xesd_ndiode_h_dnwl_X (where X=100 200 300)

DIODE

pDiode

X

lvsdiode

D

D

C

D

D

pdiode

DIODE

pDiode NV

lvsdiode

D

D

C

D

D

pdiode

DIODE

HV pDiode

X

lvsdiode

D

D

D

D

D

pdiode_h

DIODE

RF ESD HV pDiode 13

X

lvsdiode

D

D

D

D

D

D

xesd_pdiode_h_X (where X=100 200 300)

DIODE

Photo Diode

X

lvsdiode

D

D

D

D

D

D

dnwdiode_psub

DIODE

Low Vt pdiode 8

X

diode

D

D

D

D

pdiode_lvt

DIODE

High Vt pDiode 8

X

diode

D

D

D

C

D

pdiode_hvt

DIODE

High Vt pDiode NV 8

diode

D

D

D

C

C

D

pdiode_hvt

DIODE

Low Vt nDiode 8

X

diode

D

D

D

ndiode_lvt

DIODE

NV SONOS Diode 8

diode

D

D

D

D

D

ndiode_nvs

DIODE

Native nDiode 8

X

diode

D

D

D

ndiode_native

DIODE

Nwell Diode 8

X

diode

D

nwdiode

DIODE

Nwdiode_victim 17

X

lvsdiode

D

nwdiode

DIODE

Nwdiode_aggressor 17

X

lvsdiode

D

nwdiode

DIODE

RF Nwell Diode 8

X

diode

D

D

xnwdiode_rf

DIODE

Pwell-Deep Nwell Diode 8

X

diode

D

dnwdiode_pw

DIODE

RF ESD Pwell-Deep Nwell Diode 8

X

lvsdiode

D

D

D

xesd_dnwdiode_pw_X (where X=100 200 300)

DIODE

RF Pwell-Deep Nwell Diode 8

X

diode

D

D

xdnwdiode_pwell_rf

DIODE

Psub-Deep Nwell Diode 8

X

diode

D

dnwdiode_psub

DIODE

Psub-Deep Nwell Diode 17

X

lvsdiode

D

dnwdiode_psub

DIODE

Psub-Deep Nwell Diode 17

X

lvsdiode

D

dnwdiode_psub

DIODE

Psub-Deep Nwell Diode 8 19

diode

D

D

D 18

D 18

dnwhvdiode_psub

DIODE

HV Pwell-Deep Nwell Diode 8 19

diode

D

D

dnwdiode_hvpw

PNP

Parasitic PNP

X

pnp4

D

D

D

D

D

D

Layout provided by technology

pnppar pnppar5x

PNP

Parasitic HV Gated NPN

X

npn4

D

D

D

D

D

D

D

D

Layout provided by technology

npn_1x1_2p0_hv

PNP

Parasitic NPN

X

npn4

D

D

D

D

D

D

Layout provided by technology

npnpar1x1 npnpar1x2

ESD transistor

LV nESD transistor

X

nfet

D

D

D

D

NMOS with ESD_nwell_tap

nshortesd

ESD transistor

HV nESD transistor

X

nfet

D

D

D

D

D

NMOS with ESD_nwell_tap

nhvesd

ESD transistor

HV Native nESD transistor

X

nfet

D

D

D

D

D

D

NMOS with ESD_nwell_tap

nhvnativeesd

ESD transistor

HV pESD transistor

X

pfet

D

D

D

D

D

D

phvesd