SkyWater SKY130 PDK
SkyWater SKY130 PDK

Device Details

MiM Capacitor

Spice Model Information

  • Cell Name: sky130_fd_pr__cap_mim_m3__base, sky130_fd_pr__cap_mim_m4__base

  • Model Names: sky130_fd_pr__model__cap_mim, sky130_fd_pr__cap_mim_m4

Operating Voltages where SPICE models are valid

  • \(|V_{c0} – V_{c1}| = 0\) to 5.0V

Details

The MiM capacitor is constructed using a thin dielectric over metal, followed by a thin conductor layer on top of the dielectric. There are two possible constructions:

  • CAPM over Metal-3

  • CAP2M over Metal-4

The constructions are identical, and the capacitors may be stacked to maximize total capacitance.

Electrical specs are listed below:

Parameter

NOM

LSL

USL

Units

Description

CMIMA

2

1.8

2.2

fF/µm2

MiM cap area capacitance

CMIMP

0.19

0.11

0.27

fF/µm

MiM cap periphery capacitance

RSCAPM

5.8

4.8

6.8

Ω/□

MiM top plate sheet resistance

CMIM2A

2

1.8

2.2

fF/µm2

MiM2 cap area capacitance

CMIM2P

0.19

0.11

0.27

fF/µm

MiM2 cap periphery capacitance

RSCAPM

5.8

4.8

6.8

Ω/sq

MiM2 top plate sheet resistance

The symbol for the MiM capacitor is shown below. Note that the cap model is a sub-circuit which accounts for the parasitic contact resistance and the parasitic capacitance from the bottom plate to substrate.

symbol-cap_mim

Cell name

M * W * L

Calc capacitance

The cross-section of the “stacked” MiM capacitor is shown below:

cross-section-cap_mim

Varactors

Spice Model Information

  • Cell Name: :cell:`capbn_b`

  • Model Name: sky130_fd_pr__cap_var_lvt, sky130_fd_pr__cap_var_hvt

  • Model Type: subcircuit

Operating Voltages where SPICE models are valid

  • \(|V_0 – V_1| = 0\) to 2.0V

Details

The following devices are available; they are subcircuits with the N-well to P-substrate diodes built into the model:

  • sky130_fd_pr__cap_var_lvt - low VT PMOS device option

  • sky130_fd_pr__cap_var_hvt - high VT PMOS device option

The varactors are used as tunable capacitors, major e-test parameters are listed below. Further details on the device models and their usage are in the SKY130 process Family Spice Models (002-21997), which can be obtained from SkyWater upon request.

Parameter

NOM

LSL

USL

Units

Description

VC_CMAX_5_5

20.26

18.91

21.52

pF

PLOWVT based varactor 5/5 in accumulation

VC_CMAX_5_P5

10.17

9.21

11.12

pF

PLOWVT based varactor 5/5 in inversion

VC_CMIN_5_5

2.058

1.863

2.262

pF

PLOWVT based varactor 5/0.5 in accumulation

VC_CMIN_5_P5

1.9

1.725

2.087

pF

PLOWVT based varactor 5/0.5 in inversion

VC2_CMAX_5_5

20.37

19.02

21.68

pF

PHIGHVT based varactor 5/5 in accumulation

VC2_CMAX_5_P5

10.2

9.24

11.18

pF

PHIGHVT based varactor 5/5 in inversion

VC2_CMIN_5_5

4.197

3.95

4.453

pF

PHIGHVT based varactor 5/0.5 in accumulation

VC2_CMIN_5_P5

2.762

2.537

2.999

pF

PHIGHVT based varactor 5/0.5 in inversion

There is no equivalent varactor for 5V operation. The NHV or PHV devices should be connected as capacitors for use at 5V.

The symbols for the varactors are shown below:

symbol-cap_var-a symbol-cap_var-b

The cross-section of the varactor is shown below:

cross-section-cap_var

Vertical Parallel Plate (VPP) capacitors

Spice Model Information

  • Cell Name: sky130_fd_pr__cap_vpp_XXpXxYYpY_{MM}(_shield(SS)*)(_float(FF)*)(_(VVVV))

  • Model Names: sky130_fd_pr__cap_vpp_*

    • X and Y are size dimentions

    • MM refers to the layers which are used for the capacitance

    • SS refers to the layers which are used as shields (noshield when no shield is used)

    • FF refers to the layers which are floating.

    • VVVVV refers to the “variant” when there are multiple devices of the same configuration

Operating Voltages where SPICE models are valid

  • \(|V_{c0} – V_{c1}| = 0\) to 5.5V

Details

The VPP caps utilize the tight spacings of the metal lines to create capacitors using the available metal layers. The fingers go in opposite directions to minimize alignment-related variability, and the capacitor sits on field oxide to minimize silicon capacitance effects. A schematic diagram of the layout is shown below:

Todo

M3

M2

LI

M1

LAYOUT of M2, M3, M4

LAYOUT of LI and M1 (with POLY sheet)

POLY

M4

These capacitors are fixed-size, and they can be connected together to multiply the effective capacitance of a given node. There are two different constructions.

Parallel VPP Capacitors

These are older versions, where stacked metal lines run parallel:

  • sky130_fd_pr__cap_vpp_08p6x07p8_m1m2_noshield (M1 || M2 only, 7.84 x 8.58)

  • sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_noshield_o2 (M1 || M2 only, 4.38 x 4.59)

  • sky130_fd_pr__cap_vpp_02p4x04p6_m1m2_noshield (M1 || M2 only, 2.19 x 4.59)

  • sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_noshield (M1 M2, 4.4 x 4.6, 4 quadrants)

  • sky130_fd_pr__cap_vpp_11p5x11p7_m1m2_noshield (M1 M2, 11.5 x 11.7, 4 quadrants)

  • sky130_fd_pr__cap_vpp_44p7x23p1_pol1m1m2m3m4m5_noshield

  • sky130_fd_pr__cap_vpp_02p7x06p1_m1m2m3m4_shieldl1_fingercap (M1 || M2 || M3 || M4, 2.7 x 5.0)

  • sky130_fd_pr__cap_vpp_02p9x06p1_m1m2m3m4_shieldl1_fingercap2 (M1 || M2 || M3 || M4, 2.85 x 5.0)

  • sky130_fd_pr__cap_vpp_02p7x11p1_m1m2m3m4_shieldl1_fingercap (M1 || M2 || M3 || M4, 2.7 x 10.0)

  • sky130_fd_pr__cap_vpp_02p7x21p1_m1m2m3m4_shieldl1_fingercap (M1 || M2 || M3 || M4, 2.7 x 20.0)

  • sky130_fd_pr__cap_vpp_02p7x41p1_m1m2m3m4_shieldl1_fingercap (M1 || M2 || M3 || M4, 2.7 x 40.0)

The symbol for these capacitors is shown below. The terminals c0 and c1 represent the two sides of the capacitor, with b as the body (sub or well).

symbol-cap_vpp-parallel

Perpendicular VPP Capacitors

These are newer versions, where stacked metal lines run perpendicular and there are shields on top and bottom:

  • sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldm5 (11.5x11.7, with M5 shield)

  • sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldpom5 (11.5x11.7, with poly and M5 shield)

  • sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldl1m5 (11.5x11.7, with LI and M5 shield)

  • sky130_fd_pr__cap_vpp_04p4x04p6_m1m2m3_shieldl1m5_floatm4 (4.4x4.6, M3 float, LI / M5 shield)

  • sky130_fd_pr__cap_vpp_08p6x07p8_m1m2m3_shieldl1m5_floatm4 (8.6x7.9, M3 float, LI / M5 shield)

  • sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3_shieldl1m5_floatm4 (11.5x11.7, M3 float, LI / M5 shield)

  • sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3_shieldm4 (11.5x11.7, with M4 shield)

  • sky130_fd_pr__cap_vpp_06p8x06p1_l1m1m2m3_shieldpom4 (6.8x6.1, with poly and M4 shield)

  • sky130_fd_pr__cap_vpp_06p8x06p1_m1m2m3_shieldl1m4 (6.8x6.1, with LI and M4 shield)

  • sky130_fd_pr__cap_vpp_11p3x11p8_l1m1m2m3m4_shieldm5 (11.5x11.7, over 2 sky130_fd_pr__nfet_05v0_nvt of 10/4 each)

The symbol for these capacitors is shown below. The terminals c0 and c1 are the two capacitor terminals, “top” represents the top shield and “sub” the bottom shield.

symbol-cap_vpp-perpendicular

The capacitors are fixed-size elements and must be used as-is; they can be used in multiples.

Parameter

NOM

LSL

USL

Units

Description

CGGIVPPNATIVE

340.9

310.8

386

fF/cell

sky130_fd_pr__cap_vpp_11p3x11p8_l1m1m2m3m4_shieldm5_nhv, in inversion

VPP100LISM1M2M3

96.99

82.92

111.05

fF/cell

sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3_shieldl1

VPP100M1M2

74.6

57.82

91.39

fF/cell

sky130_fd_pr__cap_vpp_11p5x11p7_m1m2_noshield

VPP100M1M4M5S

108.4

92.79

124

fF/cell

sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldm5

VPP12LISM1M2M3

10.69

8.29

13.1

fF/cell

sky130_fd_pr__cap_vpp_04p4x04p6_m1m2m3_shieldl1

VPP12M1M2

7.81

6.05

9.57

fF/cell

sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_noshield

VPP1LIM1M2

0.78

0.62

0.95

fF/cell

sky130_fd_pr__cap_vpp_01p8x01p8_m1m2_noshield

VPP25PYSM1M4M5S

42.11

TBD

TBD

fF/cell

sky130_fd_pr__cap_vpp_06p8x06p1_l1m1m2m3m4_shieldpo_floatm5

VPP50LISM123M5S

42.75

33.35

50.87

fF/cell

sky130_fd_pr__cap_vpp_08p6x07p8_m1m2m3_shieldl1m5_floatm4

VPP50LISM1M2M3

TBD

34.63

50.87

fF/cell

sky130_fd_pr__cap_vpp_08p6x07p8_m1m2m3_shieldl1

VPPSYM3

35

24.5

45.5

fF/cell

sky130_fd_pr__cap_vpp_08p6x07p8_m1m2_noshield

VPPSYM4

9.48

6.64

12.32

fF/cell

xcmppp4

VPPSYM5

4.37

3.06

5.68

fF/cell

sky130_fd_pr__cap_vpp_02p4x04p6_m1m2_noshield

VPP_100_LIM5S

116.75

99.94

133.56

fF/cell

sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldl1m5

VPP_100_M3S

97.56

84.63

110.79

fF/cell

sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2_shieldpom3

VPP_100_M4S

118.5

94.82

142.2

fF/cell

sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3_shieldm4

VPP_100_M5S

137.45

117.66

157.24

fF/cell

sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldm5

VPP_100_POLYM4S

121.9

97.51

146.3

fF/cell

sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3_shieldpom4

VPP_100_POLYM5S

141.23

120.89

161.57

fF/cell

sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldpom5

Diodes

Spice Model Information

Operating regime where SPICE models are valid

  • \(|V_{d0} – V_{d1}| = 0\) to 5.0V

Details

Parameter

NOM

LSL

USL

Units

Description

BVN

11.7

10.7

14.0

V

N+ breakdown voltage

BVNH

12.7

11.7

14.0

V

HV N+ breakdown voltage

BVNE

11

9.5

14.5

V

N+ peripheral breakdown voltage

BVNEH

12.2

11.5

14.5

V

HV N+ peripheral breakdown voltage

BVP

12.2

10.2

14.5

V

P+ breakdown voltage

BVPH

12

11.2

14.5

V

HV P+ breakdown voltage

BVPE

10.5

9

14.5

V

P+ peripheral breakdown voltage

BVPEH

11.6

11.2

14.5

V

HV P+ peripheral breakdown voltage

Symbols for the diodes are shown below

symbol-diode-01 symbol-diode-02 symbol-diode-03 symbol-diode-04 symbol-diode-05 symbol-diode-06 symbol-diode-07 symbol-diode-08 symbol-diode-09 symbol-diode-10 symbol-diode-11 symbol-diode-12 symbol-diode-13 symbol-diode-14 symbol-diode-15 symbol-diode-16 symbol-diode-17

NMOS ESD FET

Spice Model Information

  • Cell Name: sky130_fd_pr__nfet_01v8

  • Model Name: sky130_fd_pr__esd_nfet_01v8, sky130_fd_pr__esd_nfet_g5v0d10v5, sky130_fd_pr__esd_nfet_g5v0d10v5_nvt

Operating Voltages where SPICE models are valid

  • \(V_{DS} = 0\) to 11.0V (sky130_fd_pr__nfet_g5v0d10v5*), 0 to 1.95V (sky130_fd_pr__nfet_01v8*)

  • \(V_{GS} = 0\) to 5.0V (sky130_fd_pr__nfet_g5v0d10v5*), 0 to 1.95V (sky130_fd_pr__nfet_01v8*)

  • \(V_{BS} = 0\) to -5.5V, (sky130_fd_pr__nfet_g5v0d10v5), +0.3 to -5.5V (sky130_fd_pr__nfet_05v0_nvt), 0 to -1.95V (sky130_fd_pr__nfet_01v8*)

Details

The ESD FET’s differ from the regular NMOS devices in several aspects, most notably:

  • Increased isolation spacing from contacts to surrounding STI

  • Increased drain contact-to-gate spacing

  • Placement of n-well under the drain contacts

Major model output parameters are shown below and compared against the EDR (e-test) specs

Param

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

IDSNESDHVS55

21.5/0.55

mA

12.172

13.073

11.277

13.144

11.207

11.46

10.57

12.35

ILKNESDHVS55

21.5/0.55

LOG A

Max = -10.8

-12.49

-15

-11.21

VTXNESDHVS55

21.5/0.55

V

0.817

0.776

0.858

0.876

0.758

0.812

0.752

0.871

IDSNESDLVS

20.35/0.165

mA

9.954

11.027

8.877

11.055

8.84

8.145

7.216

9.075

ILKNESDLVS

20.35/0.165

LOG A

Max = -10.13

-10.85

-12.15

-10.15

VTXNESDLVS

20.35/0.165

V

0.669

0.621

0.715

0.737

0.599

0.6416

0.5706

0.7125

The symbols of the sky130_fd_pr__esd_nfet_g5v0d10v5 and sky130_fd_pr__esd_nfet_g5v0d10v5_nvt (ESD NMOS FET) are shown below:

symbol-esd_nfet_g5v0d10v5 symbol-esd_nfet_g5v0d10v5_nvt

The cross-section of the ESD NMOS FET is shown below.

cross-section-esd_nfet

5.0V/10.5V NMOS FET

Spice Model Information

  • Cell Name: sky130_fd_pr__nfet_01v8

  • Model Name: sky130_fd_pr__nfet_g5v0d10v5

Operating Voltages where SPICE models are valid

  • \(V_{DS} = 0\) to 11.0V

  • \(V_{GS} = 0\) to 5.5V

  • \(V_{BS} = 0\) to -5.5V

Details

Major model output parameters are shown below and compared against the EDR (e-test) specs

Param

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXNLH

7/8

V

0.811

0.780

0.843

0.856

0.767

0.811

0.767

0.856

VTXNN42H

0.42/20

V

0.813

0.764

0.862

0.883

0.743

0.813

0.743

0.883

VTXNS50H

7/0.50

V

0.822

0.744

0.899

0.933

0.711

0.822

0.711

0.933

VTXNSN50H

0.42/0.50

V

0.781

0.672

0.891

0.937

0.625

0.781

0.625

0.937

IDSNS50H

7/0.50

mA

12.1

13.0

11.2

11.1

13.1

12.1

11.1

13.1

ILKN50H

7/0.50

LOG A

Max = -10.6

-12.3

-18

-10.9

The symbols of the sky130_fd_pr__nfet_g5v0d10v5 (5.0/10.5 V NMOS FET) is shown below:

symbol-nfet_g5v0d10v5

The cross-section of the 5.0/10.5 V NMOS FET is shown below.

cross-section-nfet_g5v0d10v5

11V/16V NMOS FET

Spice Model Information

  • Cell Name: sky130_fd_pr__nfet_extenddrain

  • Model Name: sky130_fd_pr__nfet_g5v0d16v0

Operating Voltages where SPICE models are valid, subject to SOA limitations:

  • \(V_{DS} = 0\) to +16V (\(V_{GS} = 0\))

  • \(V_{DS} = 0\) to +11V (\(V_{GS} > 0\))

  • \(V_{GS} = 0\) to 5.5V

  • \(V_{BS} = 0\) to -2.0V

Details

Major model output parameters are shown below and compared against the EDR (e-test) specs

Parameter

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXNVHV20P00P7D

20/0.7

V

0.743

0.616

0.87

0.924

0.562

0.7423

0.5612

0.9234

VTXNVHV20P02P2D

20/2.2

V

0.767

0.661

0.874

0.919

0.615

0.7668

0.6150

0.9191

IDSNVHV20P00P7D

20/0.7

mA

9.012

11.337

6.68

11.542

6.477

8.969

6.430

11.51

IDSNVHV20P02P2D

20/2.2

mA

4.444

5.56

3.329

5.657

3.232

4.440

3.232

5.656

RDSNVHV20P00P7D

20/0.7

457.3

266.1

819.4

826.4

269.6

458.5

270.3

828.2

RDSNVHV20P02P2D

20/2.2

702.8

499.7

1087.8

1097.7

498.7

703.8

499.3

1099.0

ILKNVHV20P00P7D

20/0.7

LOG A

Max = -9.01

-11.35

-18

-9.05

ILKNVHV20P00P7D

20/2.2

LOG A

Max = -9.44

-11.50

-18

-9.50

The symbol of the sky130_fd_pr__nfet_g5v0d16v0 (11V/16V NMOS FET) is shown below:

symbol-nfet_g11v0d16v0

The cross-section of the 11V/16VV NMOS FET is shown below.

cross-section-nfet_g11v0d16v0

1.8V low-VT NMOS FET

Spice Model Information

  • Cell Name: sky130_fd_pr__nfet_01v8

  • Model Name: sky130_fd_pr__nfet_01v8_lvt

Operating Voltages where SPICE models are valid

  • \(V_{DS} = 0\) to 1.95V

  • \(V_{GS} = 0\) to 1.95V

  • \(V_{BS} = +0.3\) to -1.95V

Details

Major model output parameters are shown below and compared against the EDR (e-test) specs.

Parameter

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXNLL

7/8

V

0.434

0.417

0.452

0.459

0.410

0.440

0.415

0.465

VTXNN42L

0.42/1

V

0.485

0.453

0.516

0.530

0.440

0.485

0.440

0.530

VTXNS15L

7/0.15

V

0.611

0.573

0.65

0.666

0.556

0.611

0.556

0.666

VTXNSN15L

0.42/0.15

V

0.640

0.562

0.717

0.750

0.529

0.640

0.529

0.750

IDSNS15L

7/0.15

mA

4.010

4.453

3.567

3.529

4.491

4.008

3.527

4.489

ILKN15L

7/0.15

LOG A

Max = -9.53

-10.73

-18

-9.54

Inverter Gate Delays using sky130_fd_pr__nfet_01v8_lvt/sky130_fd_pr__pfet_01v8 device combinations:

Parameter

Stages

Units

MODEL

EDR

TT

FF

SS

NOM

MIN

MAX

FO = 1

143

ps

28.61

21.96

39.15

The symbol of the sky130_fd_pr__nfet_01v8_lvt (1.8V low-VT NMOS FET) is shown below:

symbol-nfet_01v8_lvt

The cross-section of the low-VT NMOS FET is shown below. The cross-section is identical to the std NMOS FET except for the \(V_T\) adjust implants (to achieve the lower \(V_T\))

cross-section-nfet_01v8_lvt

1.8V NMOS FET

Spice Model Information

  • Cell Name: sky130_fd_pr__nfet_01v8

  • Model Name: sky130_fd_pr__nfet_01v8

Operating Voltages where SPICE models are valid

  • \(V_{DS} = 0\) to 1.95V

  • \(V_{GS} = 0\) to 1.95V

  • \(V_{BS} = +0.3\) to -1.95V

Details

Major model output parameters are shown below and compared against the EDR (e-test) specs.

Parameter

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXNL

7/8

V

0.538

0.520

0.557

0.513

0.564

0.541

0.515

0.567

VTXNN42

0.42/1

V

0.550

0.522

0.578

0.510

0.590

0.550

0.510

0.590

VTXNS15

7/0.15

V

0.645

0.615

0.677

0.603

0.689

0.700

0.661

0.739

VTSNSN15

0.42/0.15

V

0.738

0.659

0.818

0.625

0.852

0.738

0.625

0.852

IDSNS15

7/0.15

mA

3.512

3.945

3.078

3.041

3.983

3.510

3.039

3.981

ILKN15

7/0.15

LOG A

Max = -10.25

-11.31

-18

-10.69

The symbol of the sky130_fd_pr__nfet_01v8 (1.8V NMOS FET) is shown below:

symbol-nfet_01v8

The cross-section of the NMOS FET is shown below:

cross-section-nfet_01v8

The device shows the p-well inside of a deep n-well, but it can be made either with or without the DNW under the p-well

3.0V native NMOS FET

Spice Model Information

  • Cell Name: sky130_fd_pr__nfet_01v8

  • Model Name: sky130_fd_pr__nfet_03v3_nvt

Operating Voltages where SPICE models are valid for sky130_fd_pr__nfet_03v3_nvt

  • \(V_{DS} = 0\) to 3.3V

  • \(V_{GS} = 0\) to 3.3V

  • \(V_{BS} = 0\) to -3.3V

Details

The native device is constructed by blocking out all VT implants.

The model and EDR (e-test) parameters are compared below. Note that the minimum gate length for 3V operation is 0.5 µm.

Param

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXNLNVH

10/4.0

V

0.121

0.091

0.151

0.164

0.079

0.121

0.079

0.164

VTXNS90NVH

10/0.9

V

5.855

6.098

5.605

6.107

5.592

0.097

0.044

0.150

VTXNSN90NVH

0.42/0.9

V

0.075

0.017

0.129

0.152

-0.014

0.075

-0.002

0.152

IDSNS90NTH

10/0.9

mA

0.097

0.06

0.134

0.15

0.044

5.819

5.558

6.069

ILKN90NVH

10/0.9

LOG A

Max = -5.6

-6.5

-18

-5.6

VTXNS50NTH

10/0.5

V

-0.029

0.029

0.013

0.031

0.011

-0.029

-0.089

0.031

VTXNSN50NTH

0.42/0.5

V

-0.033

0.013

0.02

0.043

-0.009

-0.046

-0.142

0.050

IDSNS50NTH

10/0.5

mA

4.858

5.294

4.423

5.331

4.386

4.823

4.357

5.291

ILKN50NVH

10/0.5

LOG A

Max = -3.6

-4.03

-18

-3.67

The symbols for the sky130_fd_pr__nfet_03v3_nvt devices are shown below.

symbol-nfet_0v3v3_nvt

The cross-section of the native devices is shown below.

cross-section-nfet_03v3_nvt

Note

The only differences between the sky130_fd_pr__nfet_03v3_nvt and sky130_fd_pr__nfet_05v0_nvt devices are the minimum gate length and the VDS requirements.

5.0V native NMOS FET

Spice Model Information

  • Cell Name: sky130_fd_pr__nfet_01v8

  • Model Name: sky130_fd_pr__nfet_05v0_nvt

Operating Voltages where SPICE models are valid for sky130_fd_pr__nfet_05v0_nvt

  • \(V_{DS} = 0\) to 5.5V

  • \(V_{GS} = 0\) to 5.5V

  • \(V_{BS} = +0.3\) to -5.5V

Details

The native device is constructed by blocking out all VT implants.

The model and EDR (e-test) parameters are compared below.

The 5V device has minimum gate length of 0.9 µm.

Param

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXNLNVH

10/4.0

V

0.121

0.091

0.151

0.164

0.079

0.121

0.079

0.164

VTXNS90NVH

10/0.9

V

5.855

6.098

5.605

6.107

5.592

0.097

0.044

0.150

VTXNSN90NVH

0.42/0.9

V

0.075

0.017

0.129

0.152

-0.014

0.075

-0.002

0.152

IDSNS90NTH

10/0.9

mA

0.097

0.06

0.134

0.15

0.044

5.819

5.558

6.069

ILKN90NVH

10/0.9

LOG A

Max = -5.6

-6.5

-18

-5.6

VTXNS50NTH

10/0.5

V

-0.029

0.029

0.013

0.031

0.011

-0.029

-0.089

0.031

VTXNSN50NTH

0.42/0.5

V

-0.033

0.013

0.02

0.043

-0.009

-0.046

-0.142

0.050

IDSNS50NTH

10/0.5

mA

4.858

5.294

4.423

5.331

4.386

4.823

4.357

5.291

ILKN50NVH

10/0.5

LOG A

Max = -3.6

-4.03

-18

-3.67

The symbols for the sky130_fd_pr__nfet_05v0_nvt devices are shown below.

symbol-nfet_05v0_nvt

The cross-section of the native devices is shown below.

Note

The only differences between the sky130_fd_pr__nfet_03v3_nvt and sky130_fd_pr__nfet_05v0_nvt devices are the minimum gate length and the VDS requirements.

cross-section-nfet_05v0_nvt

20V NMOS FET

Spice Model Information

  • Cell Name: sky130_fd_pr__nfet_extenddrain

  • Model Name: sky130_fd_pr__nfet_20v0

Operating Voltages where SPICE models are valid, subject to SOA limitations:

  • \(V_{DS} = 0\) to +22V

  • \(V_{GS} = 0\) to 5.5V

  • \(V_{BS} = 0\) to -2.0V

Details

The 20V NMOS FET has similar construction to the 11V/16V NMOS FET, with several differences:

  • Longer drift region

  • Longer poly gate

  • Larger W/L

  • Devices placed in pairs (drain in center, sources on outside)

Major model output parameters are shown below and compared against the EDR (e-test) specs

Param

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXN20VHV1

2* 30/1.0

V

0.823

0.643

1.004

1.004

0.643

0.8231

0.6432

1.004

VTBN20VHV1

2* 30/1.0

V

1.823

1.573

2.075

2.075

1.573

1.823

1.573

2.075

BVN20VHV1

2* 30/1.0

V

65.96

40

80

IBB20N20VHV1

2* 30/1.0

µA/µm

0.1623

0

0.6

ID5N20VHV1

2* 30/1.0

mA

1.537

2.579

0.892

0.892

2.579

1.528

0.8892

2.556

IDLN20VHV1

2* 30/1.0

mA

0.335

0.577

0.191

0.191

0.577

0.3326

0.1903

0.5709

IDSN20VHV1

2* 30/1.0

mA

13.35

17.34

9.34

9.34

17.34

13.34

9.335

17.34

RDSN20VHV1

2* 30/1.0

327.2

195.6

562.3

562.3

195.6

327.2

195.6

562.3

RSPON20VHV1

2* 30/1.0

mΩ-mm2

98.6

58.9

169.4

169.4

58.9

98.49

59.1

137.9

ILKN20VHV1

2* 30/1.0

LOG A

Max = -8.6

-11.63

-18

-8.162

The symbol of the sky130_fd_pr__nfet_20v0 (20V NMOS FET) is shown below.

symbol-nfet_20v0

The cross-section of the 20V NMOS FET is shown below.

cross-section-nfet_20v0

20V isolated NMOS FET

Spice Model Information

  • Cell Name: sky130_fd_pr__nfet_extenddrain

  • Model Name: sky130_fd_pr__nfet_20v0_iso

Operating Voltages where SPICE models are valid, subject to SOA limitations:

  • \(V_{DS} = 0\) to +22V

  • \(V_{GS} = 0\) to 5.5V

  • \(V_{BS} = 0\) to -2.0V

Details

The 20V isolated NMOS FET has the same construction as the 20V NMOS FET, but is built over a Deep N-well. This permits the p-well to be isolated from the substrate and permit “high-side” usage (where the PW body is held above ground).

Major model output parameters are shown below and compared against the EDR (e-test) specs

Param

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXN20VHVISO1

2* 30/1.0

V

0.817

0.637

0.998

0.998

0.637

0.8171

0.6372

0.9981

VTBN20VHVISO1

2* 30/1.0

V

1.817

1.567

2.069

2.069

1.567

1.817

1.567

2.069

BVN20VHVISO1

2* 30/1.0

V

29.78

26

40

IBB20N20VHVISO1

2* 30/1.0

µA/µm

1.152

0

2

ID5N20VHVISO1

2* 30/1.0

mA

1.506

2.550

0.806

0.806

2.550

1.498

0.8033

2.526

IDLN20VHVISO1

2* 30/1.0

mA

0.336

0.578

0.174

0.174

0.578

0.3334

0.1732

0.5718

IDSN20VHVISO1

2* 30/1.0

mA

15.33

19.34

11.32

11.32

19.34

15.32

11.32

19.32

RDSP20VHVISO1

2* 30/1.0

333.7

197.9

622.4

622.4

197.9

333.7

197.9

622.4

RSPOP20VHVISO1

2* 30/1.0

mΩ-mm2

100.5

59.6

187.5

187.5

59.6

79.38

47.63

111.1

ILKN20VHVISO1

2* 30/1.0

LOG A

Max = -8.6

-11.58

-18

-8.162

The symbol of the sky130_fd_pr__nfet_20v0_iso (20V isolated NMOS FET) is shown below.

symbol-nfet_20v0_iso

The cross-section of the 20V isolated NMOS FET is shown below.

cross-section-nfet_20v0_iso

20V native NMOS FET

Spice Model Information

  • Cell Name: sky130_fd_pr__nfet_extenddrain

  • Model Name: sky130_fd_pr__nfet_20v0_nvt

Operating Voltages where SPICE models are valid, subject to SOA limitations:

  • \(V_{DS} = 0\) to +22V

  • \(V_{GS} = 0\) to 5.5V

  • \(V_{BS} = 0\) to -2.0V

Details

The 20V native NMOS FET is similar to the 20V isolated NMOS FET, but has all Vt implants blocked to achieve a very low VT.

Major model output parameters are shown below and compared against the EDR (e-test) specs

Param

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXN20VHV1L

2* 30/1.0

V

0.246

0.068

0.428

0.428

0.068

0.246

0.0676

0.4276

VTBN20VHV1L

2* 30/1.0

V

0.722

0.529

0.962

0.962

0.529

0.6321

0.436

0.8534

BVN20VHV1L

2* 30/1.0

V

58.19

40

80

IBB20N20VHV1L

2* 30/1.0

µA/µm

0.3764

0

0.6

ID5N20VHV1L

2* 30/1.0

mA

1.621

2.197

1.086

1.086

2.197

1.612

1.082

2.18

IDLN20VHV1L

2* 30/1.0

mA

0.366

0.492

0.247

0.247

0.492

0.3638

0.246

0.4872

IDSN20VHV1L

2* 30/1.0

mA

14.44

18.8

10.1

10.1

18.8

14.44

10.1

18.8

RDSP20VHV1L

2* 30/1.0

310.2

229.3

462.0

462.0

229.3

310.2

229.4

462

RSPOP20VHV1L

2* 30/1.0

mΩ-mm2

93.4

69.1

139.1

139.1

69.1

89.63

69.01

128.2

ILKN20VHV1L

2* 30/1.0

LOG A

Max = -5.6

-7.463

-9.403

-5.607

The symbol of the sky130_fd_pr__nfet_20v0_nvt (20V native NMOS FET) shown below.

symbol-nfet_20v0_nvt

The cross-section of the 20V native NMOS FET is shown below.

cross-section-nfet_20v0_nvt

20V NMOS zero-VT FET

Spice Model Information

  • Cell Name: sky130_fd_pr__nfet_extenddrain

  • Model Name: sky130_fd_pr__nfet_20v0_zvt

Operating Voltages where SPICE models are valid, subject to SOA limitations:

  • \(V_{DS} = 0\) to +22V

  • \(V_{GS} = 0\) to 5.5V

  • \(V_{BS} = 0\) to -2.0V

Details

The 20V NMOS zero-VT FET has p-well and all Vt implants blocked to achieve a zero VT.

Major model output parameters are shown below and compared against the EDR (e-test) specs

Param

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXNZVT1

2* 30/5.5

V

-0.03

-0.025

-0.024

-0.024

-0.025

-0.1224

-0.0228

-0.2228

VTBNZVT1

2* 30/5.5

V

-0.050

-0.061

0.095

0.095

-0.061

-0.0496

0.095

-0.1611

BVNZVT1

2* 30/5.5

V

48

30

80

IBBNZVT1

2* 30/5.5

µA/µm

0.033

0

0.1

ID5N0ZVT1

2* 30/5.5

mA

0.0279

0.1698

0.0035

0.0035

0.1698

0.0279

0.00354

0.1695

ID5NZVT1

2* 30/5.5

mA

1.376

1.854

0.850

0.850

1.854

1.368

0.8477

1.84

IDLN0ZVT1

2* 30/5.5

mA

0.0134

0.0689

0.0020

0.0020

0.0689

0.0134

0.00202

0.0688

IDLNZVT1

2* 30/5.5

mA

0.284

0.381

0.181

0.181

0.381

0.282

0.18

0.3777

IDSN0ZVT1

2* 30/5.5

mA

0.0336

0.2108

0.0044

0.0044

0.2108

0.0336

0.00447

0.2104

IDSNZVT1

2* 30/5.5

mA

12.85

17.50

8.35

8.35

17.50

12.79

8.366

17.38

RDSNZVT1

2* 30/5.5

365.2

271.7

589.8

589.8

271.7

365.5

271.7

589.8

RSPONZVT1

2* 30/5.5

mΩ-mm2

186.7

138.9

301.5

301.5

138.9

186.8

138.9

301.5

IOFFNZVT1

2* 30/5.5

LOG A

Max = -9.5

-11.57

-15

-9.706

The symbol of the sky130_fd_pr__nfet_20v0_zvt (20V NMOS zero-VT FET) is still under development.

The cross-section of the 20V NMOS zero-VT FET is shown below.

cross-section-nfet_20v0_zvt

Bipolar (NPN)

Spice Model Information

  • Cell Name: sky130_fd_pr__npn_05v5

  • Model Names: sky130_fd_pr__npn_05v5, sky130_fd_pr__npn_11v0

Operating regime where SPICE models are valid

  • \(|V_{CE}| = 0\) to 5.0V

  • \(|V_{BE}| = 0\) to 5.0V

  • \(I_{CE} = 0.01\) to 10 µA/µm2

Details

The SKY130 process offers “free” NPN devices. The NPN uses the deep n-well as the collector. The device is not optimized, and must be used in the forward-active mode. The following sizes of NPN’s are available:

  • ungated device with emitter 1.0 x 1.0

  • ungated device with emitter 1.0 x 2.0

  • poly-gated version with octagonal emitter of A = 1.97 µm2

The sky130_fd_pr__npn_11v0 device has a poly gate placed between the emitter and base diffusions, to prevent carrier recombination at the STI edge and increase β. The poly gate is connected to the emitter terminal.

Using this device must be done in conjunction with the correct guard rings, to avoid potential latchup issues with nearby circuitry. Reverse-active mode operation of the BJT’s are neither modeled nor permitted. E-test specs for the NPN devices are shown in the table below:

Parameter

NOM

LSL

USL

Units

Description

BFNPN1X1_10P0

37.5

18.14

56.93

NPN forward Current Gain (\(\frac{I_C}{I_B})\) at \(I_E=10 µA\)

BFNPN1X1_1P0

36.72

17.97

55.38

NPN forward Current Gain (\(\frac{I_C}{I_B})\) at \(I_E=1.0 µA\)

BFNPN1X2_17P5

35.14

16.98

53.37

NPN forward Current Gain (\(\frac{I_C}{I_B})\) at \(I_E=17.5 µA\)

BFNPN1X2_1P75

34.57

16.89

52.2

NPN forward Current Gain (\(\frac{I_C}{I_B})\) at \(I_E=1.75 µA\)

BFNPNPOLY_3P16

125.28

62.37

500

NPN forward Current Gain (\(\frac{I_C}{I_B})\) at \(I_E=3.16 µA\)

BFNPNPOLY_P316

106.98

55.94

500

NPN forward Current Gain (\(\frac{I_C}{I_B})\) at \(I_E=0.316 µA\)

VBENPN1X1_10P0

0.7745

0.7645

0.7845

V

NPN emitter-base voltage at \(I_E=10 µA\)

VBENPN1X1_1P0

0.712

0.702

0.722

V

NPN emitter-base voltage at \(I_E=1.0 µA\)

VBENPN1X2_17P5

0.7745

0.7645

0.7845

V

NPN emitter-base voltage at \(I_E=17.5 µA\)

VBENPN1X2_1P75

0.712

0.702

0.722

V

NPN emitter-base voltage at \(I_E=1.75 µA\)

VBENPNPOLY_3P16

0.7073

0.6933

0.7213

V

NPN emitter-base voltage at \(I_E=3.16 µA\)

VBENPNPOLY_P316

0.6452

0.6312

0.6591

V

NPN emitter-base voltage at \(I_E=0.316 µA\)

Symbols for the sky130_fd_pr__npn_05v5 are shown below

symbol-npn_05v0-1 symbol-npn_05v0-2 symbol-npn_05v0-3

The cross-section of the sky130_fd_pr__npn_05v5 is shown below.

cross-section-npn_05v0

The cross-section of the sky130_fd_pr__npn_11v0 is shown below. The poly gate is tied to the emitter to prevent the parasitic MOSFET from turning on.

cross-section-npn_11v0

5.0V/10.5V PMOS FET

Spice Model Information

  • Cell Name: sky130_fd_pr__pfet_01v8

  • Model Name: sky130_fd_pr__pfet_g5v0d10v5, sky130_fd_pr__esd_pfet_g5v0d10v5

Operating Voltages where SPICE models are valid

  • \(V_{DS} = 0\) to -11.0V

  • \(V_{GS} = 0\) to -5.5V

  • \(V_{BS} = 0\) to +5.5V

Details

Major model output parameters are shown below and compared against the EDR (e-test) specs

Param

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXPLH

7/8

V

-1.027

-0.971

-1.083

-0.947

-1.107

-1.027

-1.107

-0.947

VTXPN42H

0.42/20

V

-0.933

-0.886

-0.979

-0.867

-0.998

-0.93

-1.00

-0.87

VTXPS50H

7/0.50

V

-0.956

-0.889

-1.022

-0.861

-1.05

-0.954

-1.049

-0.859

VTXPSN50H

0.42/0.50

V

-0.832

-0.737

-0.927

-0.697

-0.968

-0.831

-0.967

-0.695

IDSPS50H

7/0.50

mA

7.02

7.75

6.30

6.24

7.809

6.83

6.07

7.59

ILKPS50H

7/0.50

LOG A

Max = -10.0

-10.6

-18

-10

Inverter gate delays are shown below:

Parameter

Stages

Units

MODEL

EDR

TT

FF

SS

NOM

MIN

MAX

FO = 1

79

ps

53.87

46.68

62.83

The symbols of the sky130_fd_pr__pfet_g5v0d10v5 and sky130_fd_pr__esd_pfet_g5v0d10v5 (5.0V/10.5V PMOS FET) are shown below:

symbol-pfet_g5v0d10v5 symbol-esd_pfet_g5v0d10v5

The cross-section of the 5.0V PMOS FET is shown below.

cross-section-pfet_g5v0d10v5

10V/16V PMOS FET

Spice Model Information

  • Cell Name: sky130_fd_pr__pfet_extenddrain

  • Model Name: sky130_fd_pr__pfet_g5v0d16v0

Operating Voltages where SPICE models are valid, subject to SOA limitations:

  • \(V_{DS} = 0\) to -16V (\(V_{GS} = 0\))

  • \(V_{DS} = 0\) to -10V (\(V_{GS} < 0\))

  • \(V_{GS} = 0\) to -5.5V

  • \(V_{BS} = 0\) to +2.0V

Details

Major model output parameters are shown below and compared against the EDR (e-test) specs

Param

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXPVHV20P00P66

20/0.66

V

-1.105

-1.015

-1.196

-0.975

-1.235

-1.10

-1.24

-0.98

VTXPVHV20P02P20

20/2.2

V

-1.098

-1.006

-1.189

-0.967

-1.229

-1.10

-1.23

-0.97

IDSPVHV20P00P66

20/0.66

mA

4.912

6.258

3.593

6.393

3.505

4.911

3.505

6.393

IDSPVHV20P02P20

20/2.2

mA

1.902

2.403

1.392

2.448

1.343

1.902

1.343

2.448

RDSPVHV20P00P66

20/0.66

754.8

483.1

1269.0

1274.7

481.6

757.1

482.9

1279

RDSPVHV20P02P20

20/2.2

1407

1021

2128

2163

1015

1409

1016

2167

ILKPVHV20P00P66

20/0.66

LOG A

Max = -9.66

-13.20

-14.55

-9.77

ILKPVHV20P02P20

20/2.2

LOG A

Max = -10.07

-13.20

-14.41

-10.42

The symbol of the sky130_fd_pr__pfet_g5v0d16v0 (10V/16V PMOS FET) is shown below:

symbol-pfet_g5v0d16v0

The cross-section of the 10V/16V PMOS FET is shown below.

cross-section-pfet_g5v0d16v0

1.8V high-VT PMOS FET

Spice Model Information

  • Cell Name: sky130_fd_pr__pfet_01v8

  • Model Name: sky130_fd_pr__pfet_01v8_hvt

Operating Voltages where SPICE models are valid

  • \(V_{DS} = 0\) to -1.95V

  • \(V_{GS} = 0\) to -1.95V

  • \(V_{BS} = -0.1\) to +1.95V

Details

Major model output parameters are shown below and compared against the EDR (e-test) specs

Parameter

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXPL

7/8

V

-1.107

-1.079

-1.124

-1.067

-1.141

-1.107

-1.141

-1.067

VTXPN42

0.42/8

V

-1.013

-0.974

-1.049

-0.959

-1.056

-1.023

-1.056

-0.959

VTXPS15

7/0.15

V

-0.888

-0.836

-0.940

-0.814

-0.962

-0.888

-0.963

-0.814

VTXPSN15

0.42/0.15

V

-0.819

-0.720

-0.918

-0.678

-0.951

-0.819

-0.951

-0.678

IDSPS15

7/0.15

mA

1.003

1.285

0.721

1.309

0.697

1.003

0.697

1.309

ILKP15

7/0.15

LOG A

Max = -10.7

-12

-18

-10.787

Inverter Gate Delays using sky130_fd_pr__nfet_01v8/sky130_fd_pr__pfet_01v8_hvt device combinations:

Parameter

Stages

Units

MODEL

EDR

TT

FF

SS

NOM

MIN

MAX

FO = 1

143

ps

38

29.3

52.1

The symbol of the sky130_fd_pr__pfet_01v8_hvt (1.8V high-VT PMOS FET) is shown below:

symbol-pfet_01v8_hvt

The cross-section of the high-VT PMOS FET is shown below. The cross-section is identical to the std PMOS FET except for the \(V_T\) adjust implants (to achieve the higher \(V_T\))

cross-section-pfet_01v8_hvt

1.8V low-VT PMOS FET

Spice Model Information

  • Cell Name: sky130_fd_pr__pfet_01v8

  • Model Name: sky130_fd_pr__pfet_01v8_lvt

Operating Voltages where SPICE models are valid

  • \(V_{DS} = 0\) to -1.95V

  • \(V_{GS} = 0\) to -1.95V

  • \(V_{BS} = -0.1\) to +1.95V

Details

Major model output parameters are shown below and compared against the EDR (e-test) specs

Parameter

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTCPLL

7/8

V

-0.651

-0.558

-0.744

-0.518

-0.784

-0.651

-0.785

-0.518

VTCPN42L

0.42/8

V

-0.630

-0.527

-0.733

-0.483

-0.777

-0.630

-1.042

-0.845

VTCPS35L

7/0.35

V

-0.533

-0.428

-0.638

-0.384

-0.683

-0.533

-0.683

-0.384

VTCPSN35L

0.42/0.35

V

-0.504

-0.373

-0.636

-0.316

-0.693

-8.505

-0.693

-0.316

IDSPS35L

7/0.35

mA

1.22

1.42

1.02

1.44

1.00

1.22

1.00

1.44

ILKP35L

7/0.35

LOG A

Max = -5.14

-6.671

-18

-5.144

Inverter Gate Delays using sky130_fd_pr__nfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt device combinations:

Parameter

Stages

Units

MODEL

EDR

TT

FF

SS

NOM

MIN

MAX

FO = 1

99

ps

43.4

35.9

54.8

The symbol of the sky130_fd_pr__pfet_01v8_lvt (1.8V low-VT PMOS FET) is shown below:

symbol-pfet_01v8_lvt

The cross-section of the low-VT PMOS FET is shown below. The cross-section is identical to the std PMOS FET except for the \(V_T\) adjust implants (to achieve the lower \(V_T\))

cross-section-pfet_01v8_lvt

1.8V PMOS FET

Spice Model Information

  • Cell Name: sky130_fd_pr__pfet_01v8

  • Model Name: sky130_fd_pr__pfet_01v8

Operating Voltages where SPICE models are valid

  • \(V_{DS} = 0\) to -1.95V

  • \(V_{GS} = 0\) to -1.95V

  • \(V_{BS} = -0.1\) to +1.95V

Details

Major model output parameters are shown below and compared against the EDR (e-test) specs.

Parameter

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXPLS

7/8

V

-1.050

-1.025

-1.075

-1.014

-1.086

-1.050

-1.086

-1.014

VTXPN42S

0.42/8

V

-0.941

-0.910

-0.960

-0.895

-0.983

-0.941

-0.985

-0.895

VTXPS15S

7/0.15

V

-0.781

-0.728

-0.835

-0.705

-0.858

-0.781

-0.858

-0.705

VTXPSN15S

0.42/0.15

V

-0.705

-0.599

-0.811

-0.554

-0.856

-0.705

-0.856

-0.554

IDSPS15S

7/0.15

mA

1.347

1.742

0.952

0.917

1.777

1.347

0.917

1.777

ILKP15S

7/0.15

LOG A

Max = -7.58

-10.09

-18

-7.58

Inverter Gate Delays using sky130_fd_pr__nfet_01v8/sky130_fd_pr__pfet_01v8 device combinations:

Parameter

Stages

Units

MODEL

EDR

TT

FF

SS

NOM

MIN

MAX

FO = 1

143

ps

31.8

24.7

44.1

The symbol of the sky130_fd_pr__pfet_01v8 (1.8V PMOS FET) is shown below:

symbol-pfet_01v8

The cross-section of the PMOS FET is shown below:

cross-section-pfet_01v8

20V PMOS FET

Spice Model Information

  • Cell Name: sky130_fd_pr__pfet_extenddrain

  • Model Name: sky130_fd_pr__pfet_20v0

Operating Voltages where SPICE models are valid, subject to SOA limitations:

  • \(V_{DS} = 0\) to -22V

  • \(V_{GS} = 0\) to -5.5V

  • \(V_{BS} = 0\) to +2.0V

Details

The 20V NMOS FET has similar construction to the 11V/16V NMOS FET, with several differences:

  • Longer drift region

  • Longer poly gate

  • Larger W/L

  • Devices placed in pairs (drain in middle, sources on outside)

Major model output parameters are shown below and compared against the EDR (e-test) specs

Param

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXP20VHV1

2* 30/1.0

V

-1.043

-0.843

-1.243

-1.243

-0.843

-1.043

-1.243

-0.843

VTBP20VHV1

2* 30/1.0

V

-1.588

-1.331

-1.845

-1.331

-1.845

-1.588

-1.845

-1.331

BVP20VHV1

2* 30/1.0

V

36.31

28.00

60.00

ID5P20VHV1

2* 30/1.0

mA

1.292

1.818

0.772

0.772

1.818

1.286

0.7691

1.805

IDLP20VHV1

2* 30/1.0

mA

0.261

0.367

0.157

0.157

0.367

0.26

0.156

0.364

IDSP20VHV1

2* 30/1.0

mA

11.67

16.31

6.97

6.97

16.31

11.6

6.94

16.2

RDSP20VHV1

2* 30/1.0

388.9

277.0

650.1

650.1

277.0

388.9

277.0

650.1

RSPOP20VHV1

2* 30/1.0

mΩ-mm2

82.1

58.5

137.3

137.3

58.5

82.12

58.47

137.3

ILKP20VHV1

2* 30/1.0

LOG A

Max = -8.9

-11.63

-18

-9

The symbol of the sky130_fd_pr__pfet_20v0 (20V PMOS FET) is shown below.

symbol-pfet_20v0

The cross-section of the 20V PMOS FET is shown below.

cross-section-pfet_20v0

Bipolar (PNP)

Spice Model Information

  • Cell Name: sky130_fd_pr__pnp_05v5

  • Model Names: sky130_fd_pr__pnp_05v5, sky130_fd_pr__pnp_05v5

Operating regime where SPICE models are valid

  • \(|V_{CE}| = 0\) to 5.0V

  • \(|V_{BE}| = 0\) to 5.0V

  • \(I_{CE} = 0.01\) to 10 µA/µm2

Details

The SKY130 process offer a “free” PNP device, which utilizes the substrate as the collector. This device is not independently optimized, and can be used in forward-active mode. The following sizes of PNP are available:

  • ungated device with emitter 0.68 x 0.68 (A=0.4624 µm2)

  • ungated device with emitter 3.4 x 3.4 (A=11.56 µm2)

Using this device must be done in conjunction with the correct guard rings, to avoid potential latchup issues with nearby circuitry. Reverse-active mode operation of the BJT’s are neither modeled nor permitted.

E-test specs for these devices are shown in the table below:

Parameter

NOM

LSL

USL

Units

Description

BF0P68_0P5

14.29

7.51

21.02

PNP forward current gain (\(\frac{I_C}{I_B})\) at \(I_E=0.5 µA\)

BF0P68_5

12.58

6.59

18.59

PNP forward current gain (\(\frac{I_C}{I_B})\) at \(I_E=5.0 µA\)

VBE0P68_0P5

0.7180

0.7120

0.7240

V

PNP emitter-base voltage at \(I_E=0.5 µA\)

VBE0P68_5

0.7847

0.7790

0.7904

V

PNP emitter-base voltage at \(I_E=5.0 µA\)

BF3P4_0P1

13.20

5.93

20.20

PNP forward current gain (\(\frac{I_C}{I_B})\) at \(I_E=0.1 µA\)

BF3P4_10

14.65

6.10

23.10

PNP forward current gain (\(\frac{I_C}{I_B})\) at \(I_E=1.0 µA\)

VBE3P4_0P1

0.6129

0.6087

0.6172

V

PNP emitter-base voltage at \(I_E=0.1 µA\)

VBE3P4_10

0.7351

0.7308

0.7393

V

PNP emitter-base voltage at \(I_E=1.0 µA\)

Symbols for the sky130_fd_pr__pnp_05v5 is shown below

symbol-pnp_05v0-a symbol-pnp_05v0-b

The cross-section of the sky130_fd_pr__pnp_05v5 is shown below.

No deep n-well exists in this device; the collector is the substrate.

cross-section-pnp_05v0

Generic Resistors

Generic resistors are supported in the PDK but are not recommended for analog applications. Resistor values will be extracted from the layout as long as the resistor layer is utilized, for LVS against schematic elements.

The following 3-terminal resistors are available, and have built-in diodes inside the models:

  • N+ diffusion (type “ sky130_fd_pr__res_generic_nd ”, model sky130_fd_pr__res_generic_nd )

  • P+ diffusion (type “ sky130_fd_pr__res_generic_pd ”, model sky130_fd_pr__res_generic_pd )

  • P-well (type “sky130_fd_pr__res_generic_pw”, model sky130_fd_pr__res_iso_pw)

The following 2-terminal resistors are available:

  • N+ doped gate poly (sky130_fd_pr__res_generic_po)

  • Local interconnect (sky130_fd_pr__res_generic_l1)

  • Metal-1 (sky130_fd_pr__res_generic_m1)

  • Metal-2 (sky130_fd_pr__res_generic_m2)

  • Metal-3 (sky130_fd_pr__res_generic_m3)

  • Metal-4 (sky130_fd_pr__res_generic_m4)

  • Metal-5 (sky130_fd_pr__res_generic_m5)

Specs for the generic resistors are shown below.

Parameter

NOM

LSL

USL

Units

Description

RSN

120

108

132

Ω/□

N+ diffusion sheet resistance

RSNH

114

102

126

Ω/□

HV N+ diffusion sheet resistance

RSNW

950

550

1350

Ω/□

N-Well sheet resistance

RSP

197

166

228

Ω/□

P+ diffusion sheet resistance

RSPH

191

160

228

Ω/□

HV P+ diffusion sheet resistance

RSPW

3050

2565

3535

Ω/□

P-Well sheet resistance

RSDNW

2200

1825

2575

Ω/□

Deep N-Well sheet resistance

WN

0.157

0.088

0.226

µm

Electrical N+ linewidth (drawn 0.14)

WP

0.144

0.084

0.204

µm

Electrical P+ linewidth (drawn 0.14)

RSGPVDP

48.2

42.2

55.8

Ω/□

poly sheet resistance, with NGNIT

WGPUC15

0.094

0.053

0.135

µm

Electrical poly linewidth (drawn 0.15)

RSLI

12.8

9.2

17.0

Ω/□

Local interconnect sheet resistance

RSM1

0.125

0.105

0.145

Ω/□

Metal-1 sheet resistance

RSM2

0.125

0.105

0.145

Ω/□

Metal-2 sheet resistance

RSM3

0.047

0.038

0.056

Ω/□

Metal-3 sheet resistance

RSM4

0.047

0.038

0.056

Ω/□

Metal-4 sheet resistance

RSM5

0.0285

0.0212

0.0358

Ω/□

Metal-5 sheet resistance

Symbols for all resistors are shown below:

symbol-res_generic_nd symbol-res_generic_pd

sky130_fd_pr__res_generic_nd sky130_fd_pr__res_generic_pd

symbol-res_generic_pw symbol-res_generic_po

sky130_fd_pr__res_generic_pw sky130_fd_pr__res_generic_po

symbol-res_generic_l1 symbol-res_generic_m1

sky130_fd_pr__res_generic_l1 sky130_fd_pr__res_generic_m1

symbol-res_generic_m2 symbol-res_generic_m3

sky130_fd_pr__res_generic_m2 sky130_fd_pr__res_generic_m3

symbol-res_generic_m4 symbol-res_generic_m5

sky130_fd_pr__res_generic_m4 sky130_fd_pr__res_generic_m5

P+ poly precision resistors

Spice Model Information

Operating ranges where SPICE models are valid

  • \(|V_{r0} – V_{r1}| = 0\) to 5.0V

  • Currents up to 500 µA/µm of width (preferred use ≤ 100 µA/µm)

Details

The resistors have 5 different fixed widths, plus a variable W/L option.

  • 0.35 (0p35)

  • 0.69 (0p69)

  • 1.41 (1p41)

  • 2.85 (2p83)

  • 5.73 (5p73)

They are modeled as subcircuits, using a conventional resistor model combined with the capacitance under the resistor, as well as matching parameters and temperature coefficients. The fixed-width resistors may only be used in the above configurations. Each resistor end is contacted using a slot licon. Length is variable and measured between the front ends of the slot licons.

The fixed-width resistors are modeled using the equation

*\(R_0\)* = head/tail resistance [Ω] (dominated by the slot licons)

*\(R_1\)* = body resistance [Ω/µm] = \(R_{SH}\)/W

A top-down schematic drawing of the precision resistor is shown below.

res_high_po

In addition to the \(R_0\) and \(R_1\) values, several fixed-value resistors are measured at e-test, as shown in the table below:

Parameter

NOM

LSL

USL

Units

Description

RP0P35X1SQ

964.2

593.5

1335

P+ poly resistor, 0.35 µm wide, 1 square

RP0P35X2SQ

1326

944.1

1708

P+ poly resistor, 0.35 µm wide, 2 squares

RP0P35X4SQ

2054

1624

2484

P+ poly resistor, 0.35 µm wide, 4 squares

RP0P35X20SQ

7888

6691

9086

P+ poly resistor, 0.35 µm wide, 20 squares

RP0P69NONLIN

30

25

35

%

P+ poly resistor non-linearity

RP0P69XP5SQ

575.3

366.8

783.8

P+ poly resistor, 0.69 µm wide, 0.5 square

RP0P69X1SQ

738

528

948.1

P+ poly resistor, 0.69 µm wide, 1 square

RP0P69X2SQ

1075

846.2

1303

P+ poly resistor, 0.69 µm wide, 2 squares

RP0P69X4SQ

1754

1458

2050

P+ poly resistor, 0.69 µm wide, 4 squares

RP0P69X20SQ

7201

6095

8307

P+ poly resistor, 0.69 µm wide, 20 squares

RP1P41XP5SQ

428.9

312.1

545.6

P+ poly resistor, 1.41 µm wide, 0.5 square

RP1P41X1SQ

585.9

463.8

708

P+ poly resistor, 1.41 µm wide, 1 square

RP1P41X2SQ

908.5

760.4

1057

P+ poly resistor, 1.41 µm wide, 2 squares

RP1P41X4SQ

1558

1332

1784

P+ poly resistor, 1.41 µm wide, 4 squares

RP1P41X20SQ

6764

5774

7754

P+ poly resistor, 1.41 µm wide, 20 squares

RP2P83XP5SQ

296.8

232.2

361.3

P+ poly resistor, 2.83 µm wide, 0.5 square

RP2P83X1SQ

457.1

381.5

532.8

P+ poly resistor, 2.83 µm wide, 1 square

RP2P83X2SQ

780.9

669.9

891.9

P+ poly resistor, 2.83 µm wide, 2 squares

RP2P83X4SQ

1430

1233

1627

P+ poly resistor, 2.83 µm wide, 4 squares

RP2P83X20SQ

6626

5683

7568

P+ poly resistor, 2.83 µm wide, 20 squares

RP5P73XP5SQ

236.1

195.4

276.7

P+ poly resistor, 5.73 µm wide, 0.5 square

RP5P73X1SQ

395.3

339

451.7

P+ poly resistor, 5.73 µm wide, 1 square

RP5P73X2SQ

718.2

620.9

815.6

P+ poly resistor, 5.73 µm wide, 2 squares

RP5P73X4SQ

1366

1180

1553

P+ poly resistor, 5.73 µm wide, 4 squares

RP5P73X20SQ

6556

5636

7475

P+ poly resistor, 5.73 µm wide, 20 squares

More details on the use of the precision resistors, and their models, are in the document *SKY130 process Family Device Models* (002-21997), which can be obtained from SkyWater upon request.

The symbols for the 300 ohm/sq precision resistors are shown below:

symbol-res_high_po_0p35 symbol-res_high_po_0p69

sky130_fd_pr__res_high_po_0p35 sky130_fd_pr__res_high_po_0p69

symbol-res_high_po_1p41 symbol-res_high_po_2p85

sky130_fd_pr__res_high_po_1p41 sky130_fd_pr__res_high_po_2p85

symbol-res_high_po_5p73

sky130_fd_pr__res_high_po_5p73

A generic version of the poly resistor is also available, which permits user inputs for W and L, and connections in series or parallel.

symbol-res_high_po

P- poly precision resistors

Spice Model Information

Operating ranges where SPICE models are valid

  • \(|V_{r0} – V_{r1}| = 0\) to 5.0V

  • Currents up to 500 µA/µm of width (preferred use ≤ 100 µA/µm)

Details

The resistors have 5 different fixed widths, plus a variable W/L option.

  • 0.35 (0p35)

  • 0.69 (0p69)

  • 1.41 (1p41)

  • 2.85 (2p83)

  • 5.73 (5p73)

They are modeled as subcircuits, using a conventional resistor model combined with the capacitance under the resistor, as well as matching parameters and temperature coefficients. The fixed-width resistors may only be used in the above configurations. Each resistor end is contacted using a slot licon. Length is variable and measured between the front ends of the slot licons.

The resistors are modeled using the same equations as for the P+ poly resistors. In the case of the P- poly resistors, a separate implant is used to set the sheet resistance to 2000 ohm/sq.

Fixed value resistors have the same layout footprints as their P+ poly counterparts. Electrical and e-test specs are still TBD, once sufficient silicon has been evaluated. More details on the use of the precision resistors, and their models, are in the document *SKY130 process Family Device Models* (002-21997), currently under development.

The symbols for the 2000 ohm/sq precision resistors are shown below:

symbol-res_xhigh_po_0p35 symbol-res_xhigh_po_0p69

sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69

symbol-res_xhigh_po_1p41 symbol-res_xhigh_po_2p85

sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85

symbol-res_xhigh_po_5p73

sky130_fd_pr__res_xhigh_po_5p73

A generic version of the poly resistor is also available, which permits user inputs for W and L, and connections in series or parallel.

symbol-res_xhigh_po

SONOS cells

The SKY130 process currently supports two SONOS flash memory cells:

  • The original cell is supported in the S8PFHD, S8PHRC and S8PFN-20 technology options, with operating temperatures from -55°C to +155°C

  • The “star” cell is supported in the S8PHIRS technology option. Its cell size is approximately 25% smaller than the original cell, but its temperature range is restricted to -40°C to +125°C.

Spice models for the memory cells exist for multiple conditions:

MODEL CORNERS (*.cor)

Programmed

Erased

Beginning of Life

sonos_bol_p

sonos_bol_e

End of Life

sonos_eol_p

sonos_eol_e

Program and Erase characteristics are described in more detail in the *S8 Nonvolatile Technology Spec* (001-08712), and summarized below:

Condition

\(V_G\)

\(V_D\)

\(V_B\)

\(V_S\)

\(V_{WL}\)

Pulse

Read

0

+1.1

0

0

+1.8

n/a

Program

+6.7

-3.8

-3.8

-38

Float

2 ms

Erase

-3.8

+6.7

+6.7

+6.7

Float

6 ms

VT meas

\(I_D = 2.05\)µA

+1.1

0

0

+1.8

n/a

Endurance behavior is illustrated below (100K cycles guaranteed):

sonos-erase-program

Data retention behavior is shown below at 85Csonos-data-retention

E-test parameters are summarized below for both original and star cells:

Parameter

W/L

NOM

LSL

USL

Units

Description

IDSE4522C

0.45/0.22

85

27

144

µA

SONOS erased current at Vwl=5.0

IDSE4522RC

0.45/0.22

46

20

72

µA

SONOS erased current at Vwl=1.8

IDSP4522RC

0.45/0.22

0.003

0

2

nA

SONOS programmed current at Vwl=1.8

IDSP4522RC_SP

0.45/0.22

0.003

0

0.074

nA

SONOS programmed current with Smart Program

IDSP14522RC

0.45/0.22

28

10

61.4

µA

SONOS program inhibit current, Vwl=1.8

IDSPI4522C_SP

0.45/0.22

37

15.3

83.6

µA

SONOS program inhibit current, Vwl=5.0

VTE4522C

0.45/0.22

-2.3

-3.648

-0.952

V

SONOS erased VT (VG@2.05uA)

VTP4522C

0.45/0.22

1.44

0.672

2.472

V

SONOS programmed VT (VG@2.05uA)

VTP4522C_SP

0.45/0.22

1.44

1.172

1.972

V

SONOS programmed VT with Smart Program

VTPI4522C

0.45/0.22

-1.132

-2.055

-0.512

V

SONOS program inhibit VT (VG@2.05uA)

VTPI4522C_SP

0.45/0.22

-1.132

-2.055

-0.512

V

SONOS program inhibit VT, Smart Program

IDSE3515C

0.35/0.15

0.0518

0.0162

0.103

mA

SONOS erased current at Vwl=5.0

IDSE3515RC

0.35/0.15

0.03

0.0128

0.049

mA

SONOS erased current at Vwl=1.8

IDSP3515RC

0.35/0.15

0.015

0

32

nA

SONOS programmed current at Vwl=1.8

IDSP3515RC_SP

0.35/0.15

0.015

0.001

0.172

nA

SONOS programmed current with Smart Program

IDSP13515RC

0.35/0.15

0.032

0.0089

0.0602

mA

SONOS program inhibit current, Vwl=1.8

IDSPI3515C_SP

0.35/0.15

0.032

0.0153

0.0551

mA

SONOS program inhibit current, Vwl=5.0

VTE3515C

0.35/0.15

-1.91

-3.26

-0.71

V

SONOS erased VT (VG@2.05uA)

VTP3515C

0.35/0.15

1.44

0.49

2.472

V

SONOS programmed VT (VG@2.05uA)

VTP3515C_SP

0.35/0.15

1.44

1.172

1.972

V

SONOS programmed VT with Smart Program

VTPI3515C

0.35/0.15

-1.235

-2.158

-0.415

V

SONOS program inhibit VT (VG@2.05uA)

VTPI3515C_SP

0.35/0.15

-1.235

-1.965

-0.675

V

SONOS program inhibit VT, Smart Program

The schematic for the 2-T SONOS memory cell is shown below:

schematic-sonos-cell

The cross-section of the 2-T SONOS cell is shown below.

cross-section-sonos-cell

SRAM cells

The SKY130 process currently supports only single-port SRAM’s, which are contained in hard-IP libraries. These cells are constructed with smaller design rules (Table 9), along with OPC (optical proximity correction) techniques, to achieve small memory cells. Use of the memory cells or their devices outside the specific IP is prohibited. The schematic for the SRAM is shown below in Figure 10. This cell is available in the S8 IP offerings and is monitored at e-test through the use of “pinned out” devices within the specific arrays.

figure-10-schematics-of-the-single-port-sram

Figure 10. Schematics of the Single Port SRAM.

A Dual-Port SRAM is currently being designed using a similar approach. Compilers for the SP and DP SRAM’s will be available end-2019.

Operating Voltages where SPICE models are valid

  • \(V_{DS} = 0\) to 1.8V

  • \(V_{GS} = 0\) to 1.8V

  • \(V_{BS} = 0\) to -1.8V

Details

N-pass FET (SRAM)

Spice Model Information

  • Cell Name: sky130_fd_pr__nfet_01v8

  • Model Name (SRAM): sky130_fd_pr__special_nfet_pass

Parameter

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXNPAS

0.14/0.15

V

0.68

0.52

0.846

0.846

0.515

0.669

0.498

0.839

IDSNPAS

0.14/0.15

µA

0.0702

0.0948

0.0471

0.0943

0.0473

68.2

45.5

90.8

ILKNPAS

0.14/0.15

LOG A

Max = -8.0

-9.73

-12.33

-9.1

N-latch FET (SRAM)

Spice Model Information

  • Cell Name: sky130_fd_pr__nfet_01v8

  • Model Name (SRAM): sky130_fd_pr__special_nfet_latch

Parameter

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXNLTC

0.21/0.15

V

0.715

0.574

0.856

0.856

0.575

0.709

0.567

0.851

IDSNLTC

0.21/0.15

µA

0.091

0.1197

0.0616

0.1192

0.0618

87.9

60.2

115.5

ILKNLTC

0.21/0.15

LOG A

Max = -7.8

-9.45

-11.65

-8.90

P-latch FET (SRAM)

Spice Model Information

  • Cell Name: sky130_fd_pr__pfet_01v8

  • Model Name (SRAM): sky130_fd_pr__special_pfet_pass

Parameter

W/L

Units

MODEL

EDR

TT

FF

SS

FS

SF

NOM

MIN

MAX

VTXPLTC

0.14/0.15

V

-0.918

-0.761

-1.085

-0.747

-1.089

-0.905

-1.080

-0.732

IDSPLTC

0.14/0.15

µA

0.0208

0.0306

0.0113

0.0304

0.0113

19.9

10.7

29.1

ILKPLTC

0.14/0.15

LOG A

Max = -7.3

-9.860

-13.31

-8.880

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